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we are looking for a CPU Verification Technical Lead, Google Cloud
Responsibilities
Plan the verification strategy, identify the platform to validate reasoning components.
Define the test plan and strategy with stakeholders, including sign-off and exit criteria.
Plan and execute the verification of Internet Protocols (IPs) using dynamic verification and formal verification.

we are looking for a SoC Verification Technical Lead, Google Cloud
Responsibilities
Plan the verification strategy, identify the platform to validate reasoning components.
Define the test plan and strategy with stakeholders, including sign-off and exit criteria.
Plan and execute the verification of Internet Protocols (IPs) using dynamic verification and formal verification.

we are looking for a Senior CPU Architect, Google Cloud
Responsibilities
Lead architectural definition of CPU core designs, facilitate and make final decisions.
Participate in and influence the building of processor performance analysis infrastructure.
Influence the development of architectural models with varying configurations across product categories.
Perform Performance, Power, Area (PPA) trade-off analysis for architecture and microarchitecture features, communicate analysis results in both qualitative and quantitative fashion to support decisions.

In this role, you will work with system teams and the CPU Architecture team to develop an understanding of the CPU, System on a Chip (SoC), performance metrics, benchmarks/measuring tools, and available optimization knobs. You will define methods and technologies to model CPU performance at different accuracy levels by supporting architectural explorations and decision-making. You will correlate performance projections with measured post-silicon data.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
Responsibilities
Write product or system development code.
Design, develop, test, deploy, maintain, and improve Central Processing Unit (CPU) software modeling and other software tools.
Manage project priorities, deadlines, and deliverables.
Collaborate with hardware and software CPU architecture teams, SOC performance modeling team, and other Google Software teams.

we are looking for a Formal Verification Engineer, Networking, Google Cloud
Responsibilities
Plan the formal verification strategy and create the properties and constraints for digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.

Why Join Us?
We are seeking a highly skilled Technical Project Manager with a strong background in software development and hardware engineering to join our Firewall Core Group. The ideal candidate will have experience managing complex, cross-functional projects that span both hardware and software domains, with a focus on delivering new products and releases for our company's Security Gateways.
Key Responsibilities
Lead cross-functional hardware/software projects, managing new product development and releases for our company's Security Gateways.
Oversee the entire project lifecycle, from planning to execution and delivery.
Manage board design, hardware development, and prototype builds (EVT, DVT, PVT) with contract manufacturers.
Coordinate multiple interfaces, including R&D, QA, PMO, and Product Management.
Drive software release processes, infrastructure changes, and quality improvements.
Ensure smooth project execution by maintaining schedules, mitigating risks, and managing external vendors.

In this role, you will help to develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our Application-specific integrated circuit (ASIC) projects. You will provide emulation infrastructure and methodologies for supporting these projects. You will work with other emulation team members as well as designers, verification engineers, and software teams. You will work with with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, assisting in the hardware and lab bring up, and verification of our ASIC systems.

Responsibilities
Help in maintaining and upgrading emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in Google infrastructure.
Support emulation team members with debugging hardware, tooling, and project specific issues.
Help to bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms, and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

we are looking for a Senior SOC and IP Design Engineer, Google Cloud
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

we are looking for a Senior SOC RTL Design Engineer, Google Cloud
Responsibilities
Define the SOC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC level verification.
Communicate and work with multi-disciplined and multi-site teams.

We are looking for an experienced Product Manager to lead our SW product development efforts. In this role, you will work cross-functionally to collect inputs from the market (research, customers and internal sources) and guide R&D Software, Firmware, Post processing and DSP teams from conception to launch, ensuring alignment with our business strategy and customer needs. You will be responsible for driving innovation and managing the product lifecycle. The ideal candidate will have a strong development background, experience working in fast evolving startup environments and agility.
This is a hands-on role: youll deep dive into product technical details, focusing mainly in bound activities, work with R&D teams to prioritize, while maintaining our customers needs and meeting their requirements.
Responsibilities:
Lead the strategy, and execution of the software, firmware, post processing and DSP products, ensuring it aligns with overarching business goals.
Serve as the voice of the business, ensuring the product team delivers measurable KPI and meets market and customer demands.
Partner closely with stakeholders in R&D, and business teams to align product development with business objectives.
Collaborate & prioritize with R&D teams to deliver high-quality perception Radar-AI based products.
Partner closely with the customer management to collect inputs from customers and communicate offering to the customers.

Were looking for a talented and driven Integration Team Lead to join our System Engineering group. In this role, youll lead the integration team, working closely with system engineers, V&V, and other R&D functions to bring cutting-edge technologies into reality.
Responsibilities:
Lead and manage the integration team, including task planning, setting priorities and mentoring team members
Be the technical focal point for integration-related activities
Oversee system testing and manage the handover process from Integration to V&V
Lead system bring up activities
Responsible for troubleshooting efforts and resolving problems in a timely manner
Maintain a broad understanding of the entire system and stay up to date with the latest version
Lead by example, motivate, empower and develop team members to reach their full potential
Establish strong working relationships with System Engineering and V&V teams to ensure high-quality delivery
Collaborate closely with multiple cross-functional teams across the organization

we are seeking a motivated and detail-driven Safety Compliance Practical Engineer to support our compliance with ISO 26262 standards across the entire R&D lifecycle. Working under the supervision of the Senior Safety Compliance Engineer, this role plays a critical part in guiding development teams, ensuring traceability, and aligning safety work products with functional safety (FuSA) requirements. This is a hands-on position suited for individuals who are technically curious, process-oriented, and ready to grow into a functional safety role through practical experience and close mentorship.
Responsibilities:
Support the implementation of ISO 26262 activities across all development phases from concept through validation ensuring consistent compliance.
Guide R&D teams in preparing and structuring ISO 26262-compliant documentation.
Create and maintain safety-related work products, reports, and checklists.
Ensure traceability between safety requirements and development artifacts using Polarion.
Provide compliance-oriented input during design reviews to ensure safety alignment.
Identify gaps and risks related to safety documentation and traceability.
Maintain close, end-to-end interaction with all relevant teams to embed safety considerations throughout the development lifecycle.
Participate in interactions with external certification bodies as needed.
Progressively take ownership of safety tasks with increasing autonomy under supervision.

Were looking for a talented Lab Manager to join our R&D System group.
Responsibilities:
Build setups and maintain those including RF and digital
Participate and support with any lab work of performing measurements, recording, etc
Understand the development team's needs and enable specific lab setups, measurements, etc
Equipment calibration and support
Responsibility for the SW images of the labs PC and chambers
Enable and maintain remote workstations
Work with IT and DevOps to enable fluent and secured work in the labs
Manage the labs and the chambers calendar, ESD, ISO, equipment, etc
Responsible for lab equipment including ordering of small equipment and measurements equipment

We are looking for a Product & Test ATE Engineer.
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ , Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will be responsible for performance analysis for a networking stack using the knowledge of Remote Direct Memory Access (RDMA) based transports.

Responsibilities
Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how everything interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro-architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.