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As a Wireless SOC Design Verification Engineer, you'll be at the heart of the chip design effort - owning a meaningful verification scope and growing it project to project.
You'll work alongside DV methodologists, designers, architects, communication systems engineers, and firmware engineers to build reusable testbenches and verification environments using the latest metric-driven verification methodology.

You'll be responsible for pre-silicon RTL verification at the block, subsystem, and top-level SOC, taking your scope from test planning through coverage closure and signoff.
Your activity may focus at block level, subsystem level, or top-level SOC, including end-to-end simulations of the entire data/control path.

Responsibilities
Own critical block, subsystem, and top-level SOC verification scope on wireless SOC projects
Architect and develop testbenches and verification environments using state-of-the-art, metric-driven verification methodologies
Define the verification plan; create, simulate, and debug test scenarios
Drive regression and coverage analysis to ensure high-quality DV
Collaborate with design and systems engineering teams to review requirements, specifications, and architecture - extracting features and defining DV attributes
Verify power intent using UPF within your area; low power is part of your scope wherever it shows up
Over time, you can grow deeper into the IPs and subsystems you know best, or broader - across IPs and up from block level to full SOC integration.
The team is also pushing hard on AI-assisted verification, and you'll help figure out where it fits best: test generation, debug, coverage closure, or all of the above.

Play a part in shaping the future of human-computer interaction. We're looking for an Engineering Program Manager (EPM) to turn advanced machine learning in speech, audio and computer vision into features that ship to customers.
You'll work across ML research, data collection, silicon, FW, and the device and companion SW teams that bring these features to our customers. Your work will cover every stage, from the first dataset to the final release.

You'll own the plan for taking ML features from research to release. That covers data planning, model training and evaluation, optimization for our silicon, integration with SW teams, and release. You'll keep teams aligned, make risk visible early, and help leadership decide when model quality, performance and schedule pull in different directions. You'll be comfortable with how uncertain research is, and disciplined about delivering what ships.

Responsibilities
Own the delivery plan for ML features, from research and prototyping through integration, validation and release.
Partner with data teams to build the data strategy and plan, making sure it covers what the models need and supports program milestones: what data, at what scale and coverage, and by when.
Align model milestones with HW builds, pre-silicon validation (simulation and FPGA), and silicon bring-up, ensuring models are ready at each gate.
Lead integration with SW groups, including model handoff, interfaces, integration schedules and release timing.
Align ML teams, MLOps and data science on priorities, compute capacity and dependencies.
Track model quality, latency, memory and power against product targets, and lead trade-off decisions.
Set up model release practices: readiness gates, versioning, regression tracking and post-integration monitoring.
Summarize ML progress into clear, data-driven recommendations for leadership.

We're looking for an Engineering Program Manager (EPM) to lead a multidisciplinary program that takes a new sensing technology from research to product. The program covers HW, sensing, mechanical engineering, FW, SW, and ML. You will turn early research into a roadmap that can ship, and keep the teams aligned around one goal: a new kind of interaction experience for our users.
This is not a typical execution role. You'll work closely with researchers and engineers while driving and supporting execution. You'll know when to give exploration room and when to push toward productization. You'll be fluent in both scientific uncertainty and product discipline.

You'll be the central point of coordination for a program that moves through research, feasibility, prototyping, and product development at the same time. Working with world-class scientists, engineers, and ML experts in Israel and the US, you'll define the plan, make technical risk visible, and help leadership make clear decisions when the path forward isn't obvious. Along with engineering leadership, you'll be the face of the program.

Responsibilities
Build and own the program roadmap, from research milestones and feasibility checkpoints through prototype builds and productization.
Turn open-ended research questions into structured plans with clear hypotheses, success criteria, and decision gates.
Summarize research results into clear, data-driven findings and recommendations for executive audiences.
Keep a collaborative, transparent culture that respects research rigor and product urgency equally.
Align cross-functional teams across HW, physics, optics, mechanical, FW, ML/algorithms, data collection, and user experience.
Manage dependencies between ML workstreams, data collection, and HW development so learning cycles stay fast.
Run prototype and development builds with engineering teams, operations partners, and suppliers.
Spot technical and organizational risks early, and present them as strategic choices with mitigation paths.
Keep a collaborative, transparent culture that respects research rigor and product urgency equally.
Improve program methods to fit the needs of a research-to-product program.

We are looking for a Software Engineering Manager to lead the SW Tools & Automation team in our Cellular group in Herzliya. The team builds and runs the engineering backbone of Cellular RF validation. You will be in charge on a variety of domains: Validation environments, CI/CD and lab automation infrastructure, the data path (lab results), & a broad set of tools for test execution, results analysis and lab monitoring.
As manager, you will own the team's technical vision and its people. You will turn the needs of many engineering teams into a clear roadmap and make sure what we deliver is reliable, scalable and actually used.
You will inherit an established, high-impact team with a broad, mature portfolio, backed by a world-class organization. You will be able to shape the direction of systems used across our cellular validation, work with talented colleagues in Israel and around the world, and grow your own career within us.

As a Construction Project Manager supporting the Israel market, youll be a key point of contact for project delivery, taking complex projects from initial concept through due diligence, design, construction, commissioning, and handover across sites in Israel, primarily in Herzliya, Haifa, and Jerusalem.

Youll own ambiguous challenges as they arise, drive cross-functional alignment, and help enforce quality, schedule, and cost controls. The ideal candidate is a proactive problem-solver who coordinates effectively with a diverse group of stakeholders - including leadership, internal R&D/engineering partners, architects and the Global Design Team, engineers, corporate procurement, global security, IT & AV teams, vendors, suppliers, and general contractors - to deliver functional, high-quality spaces on time and within budget.
Responsibilities
Scope & Strategy: Translate end-user and scientific requirements into actionable design criteria, defining project scope, milestones, and deliverables in partnership with key stakeholders. Use Apple devices, iOS, and internal software within Apples environment and network.
Planning & Procurement: Develop project execution plans (budgets, schedules, risk mitigation) and lead selection and management of architects, third-party PM and supervision firms, engineers, general contractors, and specialty trade vendors.
Design & Technical Integration: Oversee the design development process to preserve architectural intent while coordinating complex MEP and process utility systems critical to lab environments (e.g., HVAC, process piping/gases, clean dry air, tooling hookups, high-voltage capacity, UPS and generators).
Site Leadership & Craftsmanship: Serve as the on-site owners representative, monitoring work progress, identifying risks, and upholding standards for health, safety, schedule discipline, and finish quality befitting Apples high-design environments.
Project Controls & Financials: Manage project budgets, cost forecasting, contractor billing, and change orders, proactively flagging and addressing cost and schedule variances.
Permitting & Compliance: Lead local authority approvals, environmental health and safety requirements, and municipal permitting processes.
Handover & Operational Readiness: Coordinate transitions to facilities and end-users, including commissioning, punch lists, occupancy permits, and documentation handover (as-builts, warranties, O&M).

The Cellular group is looking for an extraordinary Cellular-RF Post-Silicon Validation Engineer. In this role you will be responsible for developing and executing comprehensive RF validation strategies for cellular silicon products, conducting meticulous RF performance, analyzing complex measurement data and collaborating with cross-functional teams to identify and resolve silicon design issues. You will leverage your deep understanding of RF system parameters, measurement methodologies and cellular standards to ensure products meet rigorous quality and performance specifications throughout the development lifecycle.

We are looking for a Privacy Preserving Engineer who combines strong machine learning fundamentals with practical software engineering skills. This is an applied, hands-on engineering role: you will work closely with theoretical researchers to deeply understand their mathematical formulations, understand the core contributions of their work, and modify the heart of our training pipelines and models accordingly.

Responsibilities
Translate advanced mathematical theory, privacy mechanisms, and research formulations into robust, practical machine learning systems.
Dive deep into core model training loops (in PyTorch) to modify, inject, and optimize custom components, loss functions, clipping mechanisms, and private optimizers.
Design, architect, and implement end-to-end privacy-preserving machine learning pipelines.
Evaluate privacy-utility trade-offs, measuring model accuracy, convergence behavior, and empirical privacy leakage.
Collaborate closely with theoretical research scientists to validate algorithmic hypotheses and verify theoretical guarantees in practical setups.
Package, document, and present research implementations, technical prototypes, and proof-of-concepts clearly to cross-functional teams and leadership
Stay updated o.n modern privacy-enhancing technologies and open-source differential privacy tooling.

The Pixel DV group works on complex, large-scale media IPs. We partner with our architecture and design teams to deliver high quality media IP and systems in order to meet the demanding requirements for excellent products, while boosting performance and meeting area and power goals, incorporating new high quality features.

You will develop verification test plans, test benches, tools and infrastructure, protocol monitors and agents, and coverage driven stimulus.
Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market.
Apply deep system level understanding to find system architecture bugs, verifying the DUT at multiple levels - from block level to the entire IP and subsystem, with additional emphasis on power (NLP) and performance.
You will work closely with the design and architecture teams from the early stages of feature definition, to ensure timely delivery of quality designs.
Working with methods to accelerate verification time.
Involvement with Post Silicon Validation and other verification teams.
Candidate should have good interpersonal and collaboration skills, to work with our partner Design and Architecture teams

In this highly visible role, you will be working with the elite CPU and SOC teams which powers products that are exceptionally efficient and exceptionally performant. You will be at the center of a chip design effort interfacing with all disciplines spread across multiple geographies, with a critical impact on getting functional products to millions of customers quickly.

The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Play a critical role in end-to-end verification of memory subsystem by developing an in-depth understanding of cache coherence protocols and functioning of various units in CPU/SOC that are relevant to memory subsystem verification. These units include Load-Store unit, different levels of caches, bus interface units, memory controller, etc.
Develop verification environment which can be used in both simulation and emulation.
Develop synthesizable transactors and test benches and support verification hooks for verifying memory subsystem functionality and CPU/SOC features.
Develop unit level stimulus as well as full chip assembly or C programs to verify memory subsystem functionality.
Develop verification IPs that can be utilized by Apple teams worldwide
Work closely with the CPU/SOC RTL spread across US and Israel to understand the specification in detail for developing verification strategy taking system level considerations into account.
Develop coverage monitors and accomplish coverage goals for closure of the design.
Develop abstract end-to-end checks to verify CPU-SOC memory subsystem interaction and coherence protocols

As a RTL Engineer, you will own or participate in the following:
* Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification.
* RTL feature ownership - development, assessment and refinement of new RTL features to target power, performance, area and timing goals.
* Validation - support test bench development and simulation for functional and performance verification.
* Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance.
* Design delivery - work with multifunctional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power.

In this role you'll participate in the architecture of next generations of our ISP, handle RTL implementation of the micro-architecture, participate in clearly defining specification, testing and verification of the designs. You will work in collaboration with CAD & PD teams to implement RTL design into GDS, run various flows and provide guidelines to other designers and participate in establishing CAD and design methodologies for correct by construction designs.
Were not all the same. And thats our greatest strength. We draw on the differences in who we are, what weve experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.

Responsibilities
As a logic design engineer, you will handle micro architecture & RTL implementation as well as front-end work and top-level aspects of the design, such as performance and more. You will work closely with DV teams to verify blocks and SoCs and with PD for design implementation.

As a formal verification technical lead you'll work to identify targets and complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.).

Responsibilities
You will be responsible for: Working with our world-classP design engineers to develop a formal micro-architecture specification. Formalizing the refinement from architecture to micro-architecture. Developing comprehensive formal verification test plan. Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture. Crafting novel and creative solutions for verifying complex design micro-architectures. Developing and implementing re-usable and optimized formal models and verification code base. Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.

Our team is looking for an experienced and highly motivated Team Lead Software QA who is passionate about delivering exceptional product quality. You will lead a team of QA engineers validating complex products that combine software, hardware, backend services, mobile applications, and cloud infrastructure. You will set the quality strategy, develop your team, and take ownership of quality from feature design through customer delivery. We are looking for someone who enjoys understanding complex systems and can quickly move between software, hardware, and infrastructure.

Responsibilities
Leadership and team management:
Lead, mentor, and develop a team of QA engineers, including hiring, onboarding, performance feedback, and career growth.
Plan and prioritize the teams work across multiple projects and releases
Represent QA in planning, design, and release decisions, and report quality status and risks to stakeholders.

Quality ownership:
Own the quality effort for features and projects from design through release
Define test plans, test cases, and validation strategies.
Continuously improve testing methodologies, processes, and product quality.
Drive high product quality while continuously improving the customer experience.

Hands-on technical work:
Validate software functionality across backend services, mobile applications, desktop applications, and hardware components.
Oversee functional, regression, integration, end-to-end, and system-level testing.
Investigate, reproduce, and triage complex software and hardware issues.
Analyze logs, system behavior, and test results to identify root causes and clearly communicate findings.
Work with databases to validate data integrity and troubleshoot backend issues.
Use command line tools and shell environments.

Responsibilities
Help create the next line of our AI products by leading the build of the infrastructure and groundwork they will stand on.
Lead the architecture and delivery of the low-latency middleware layer behind our iOS and macOS data collection and research applications.
Stay hands-on: write code, review pull requests, and debug the hard problems alongside the team. This is not a purely managerial role.
Set technical direction and coding standards across C++, Objective-C/C++, Swift, and Python.
Own the roadmap with research, firmware, silicon, and product partners, and turn ambiguous, ambitious goals into a concrete technical plan.
Drive design and implementation decisions for the applications on top of the middleware, not just the layer underneath.
Mentor and grow a team of strong engineers, and run the design and code reviews that set the culture.
Bring AI-assisted development into the teams daily workflow and show how much a small team can ship.
Work across the whole stack, from high-level software to low-level physics, and connect the disciplines that make it work.