As a Wireless SOC Design Verification Engineer, you'll be at the heart of the chip design effort - owning a meaningful verification scope and growing it project to project.
You'll work alongside DV methodologists, designers, architects, communication systems engineers, and firmware engineers to build reusable testbenches and verification environments using the latest metric-driven verification methodology.
You'll be responsible for pre-silicon RTL verification at the block, subsystem, and top-level SOC, taking your scope from test planning through coverage closure and signoff.
Your activity may focus at block level, subsystem level, or top-level SOC, including end-to-end simulations of the entire data/control path.
Responsibilities
Own critical block, subsystem, and top-level SOC verification scope on wireless SOC projects
Architect and develop testbenches and verification environments using state-of-the-art, metric-driven verification methodologies
Define the verification plan; create, simulate, and debug test scenarios
Drive regression and coverage analysis to ensure high-quality DV
Collaborate with design and systems engineering teams to review requirements, specifications, and architecture - extracting features and defining DV attributes
Verify power intent using UPF within your area; low power is part of your scope wherever it shows up
Over time, you can grow deeper into the IPs and subsystems you know best, or broader - across IPs and up from block level to full SOC integration.
The team is also pushing hard on AI-assisted verification, and you'll help figure out where it fits best: test generation, debug, coverage closure, or all of the above.
Requirements: Minimum Qualifications
BS in Electrical Engineering or Computer Engineering.
Solid problem-solving and debugging skills with constrained-random verification.
Understanding of digital logic design, SOC architecture, and microarchitecture.
Self-motivated and dedicated, with proven creative thinking capabilities.
Ability to handle multiple tasks and priorities work to meet deadlines.
Preferred Qualifications
Hands-on experience across the verification cycle: test planning, testbench implementation, test creation and debug, and coverage closure.
Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM and DV methodologies.
Great teammate with excellent communication skills and the desire to take on diverse challenges.
Experience taking at least one ASIC/SOC from concept through tape-out
Experience with MAC or PHY verification.
Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols.
Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment.
Experience with low-power verification, UPF, boot-up, power-cycling, and HW/FW interaction.
Experience with SystemVerilog Assertions (SVA) and/or formal tools (e.g., JasperGold).
Experience defining coverage space and writing coverage models.
Experience with embedded CPU verification; programming in C/C++ or assembly.
Scripting in Python or Perl; interest in applying AI/ML to verification workflows.
This position is open to all candidates.