דרושים » הנדסה » Junior Wireless SoC Design Verification Engineer

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Description
- Own critical block and sub-system verification of wireless SoC projects.
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies.
- Define verification plan, create, simulate and debug test scenarios.
- Drive regression and coverage analysis to ensure high quality DV.
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute.

As a formal verification technical lead you'll work to identify targets and complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.).

Responsibilities
You will be responsible for: Working with our world-classP design engineers to develop a formal micro-architecture specification. Formalizing the refinement from architecture to micro-architecture. Developing comprehensive formal verification test plan. Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture. Crafting novel and creative solutions for verifying complex design micro-architectures. Developing and implementing re-usable and optimized formal models and verification code base. Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.

As a member of our Physical Design team in this highly visible role, you will directly own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.
* Implementation - Block level PnR, floor-planning, clock, power planning and distribution.
* Verification and Analysis - Static Timing closure using commercial tools, Physical Verification as well as Electrical/Power Analysis (EM / IR-Drop / Xtalk / noise )

As member of the DV CAD team, you have the opportunity to impact our engineers who develop next generation of our products!
You will be responsible for developing software solutions used by thousands of DV engineers globally. You will be supporting design process of all chip families we make (iPhone, iPad, Mac, our Watch and more), and your work will help streamline this complex process. This role combines DV knowledge alongside modern software engineering practices. Your work will be very diverse, and you will have broad impact contributing to the success of us.


You will develop and drive software development of multiple tools across the DV space, including cloud-native services, GUI, LLM harness, CI/CD. Your work will span from software development and architecture to collaborating with DV engineers, working with EDA vendors, and supporting critical project milestones.

Responsibilities
Developing and maintaining LLM harness for agentic DV workflows, and being responsible for benchmarking and improving accuracy of agentic workflows.
Building and managing cloud-native services running on k8s, including CI/CD, containerization, alerting, databases, GUI and monitoring.
Communication with DV stakeholders and working to understand user requirements.
Writing and maintaining Python scripts used as part of design simulation flows.
Supporting multiple projects simultaneously.

We are seeking talented, creative and disciplined engineers to join the best-in-class team that plays a significant part in the development of new silicon for our eco-systems by engaging in a dynamic, highly collaborative environment with the focus on the following goals.

Deep understanding of components/modules within wireless communication systems and the corresponding calibration and impairment reduction techniques - Develop methods/algorithms to alleviate hardware induced impairments by calibration, cancellation and other applicable techniques - PHY firmware architecture and design, including calibrations, real-time processing flows, collaboration with RF hardware, microcode, and MAC layer.

Develop highly efficient designs delivering outstanding performance, optimizing power and memory footprints while meeting hard-realtime latency requirements.

Debug real-time systems with limited visibility, working hands-on with development boards and lab equipment.

Collaborate with Radio, MAC, and Systems engineering teams to architect, define and implement innovative algorithms, calibrations, and protocols.

Support pre-silicon validation efforts, including simulation, emulation, and FPGA prototyping.

Develop SoC test and calibration capabilities for chip, module, and product factories.

Support post-silicon bringup, validation, performance characterization, system integration and debugging. - Repeatedly measure and optimize results using various test harnesses - Automate calibration and verification processes

We're seeking a passionate and skilled Embedded Firmware Engineer to play a pivotal role in delivering the next generation of us. In this highly visible position, you'll be at the intersection of hardware and software, collaborating closely with logic designers to deeply understand system-level operations and performance requirements for hardware validation. In this role, you will develop critical low-level embedded firmware specifically designed to validate hardware functionality, ensure conformance, and drive performance during the bring-up and testing phases of new silicon. This involves designing, developing, and integrating complex drivers, diagnostic tests, and infrastructure essential for SoC bring-up, post-silicon validation, and debugging activities. Ultimately, you'll lead hands-on firmware development, system-level validation, and problem-solving at the hardware-software interface in a dynamic, collaborative environment, with your work directly enabling the successful launch of future products by ensuring our silicon meets the highest standards.

We are looking for experienced Chip Design Engineers to join our team and take a key role in RTL design, new IP development, and SoC integration.

As part of the design team, you will be deeply involved in architectural exploration, protocol evaluation, and hands-on design work across multiple chip blocks.

Responsibilities
RTL design and implementation of new IPs.
SoC integration and design ownership of chip subsystems.
Exploration and evaluation of new protocols and architectural solutions.
Close collaboration with architecture, verification, validation, software, and back-end teams.
Delivering high-quality, best-in-class RTL that meets performance, power, and area goals.

We are seeking an experienced SOC Validation Team Leader to lead the system validation team activities for our next-generation BMC (Baseboard Management Controller) SoCs, widely used in enterprise and data center servers.

Responsibilities:

Lead a team of experienced system and validation engineers, including hands-on involvement.
Define and execute validation strategies for complex SoC products across pre- and post-silicon stages.
Collaborate closely with HW, Embedded SW, Architecture, and Security teams to ensure full system coverage.
Analyze product requirements and define comprehensive validation plans and methodologies.
Develop and maintain validation environments, including test frameworks, automation, and infrastructure.
Drive debug and root-cause analysis of system-level issues across HW/SW boundaries.
Ensure high-quality validation coverage and sign-off aligned with product and customer requirements.
Support pre-silicon activities (emulation, FPGA) and post-silicon bring-up and system validation.
Drive continuous improvements in validation processes, tools, and productivity.
Mentor and support team members in technical growth and execution excellence.
Participate in recruitment and onboarding of new team members.

We are seeking a highly skilled Emulation Engineer with extensive experience in the semiconductor industry to join our Chip Design team.

The ideal candidate will have a proven track record working with advanced emulation platforms, particularly Veloce, Palladium or Zebu.

Key Responsibilities:
Develop and maintain emulation models from RTL for complex SoC designs
Port RTL designs into emulation platform.
Debug hardware and software issues in pre-silicon environments.
Collaborate with frontend design, design verification, validation and software development teams to create comprehensive test strategies.
Set up and maintain emulation hardware infrastructure.
Develop workflows for efficient emulation processes.
Collaborate with emulator vendor field service engineers to resolve hardware issues.
Support users and debug issues.

As a manager in the RTL/FE CAD team, you have the opportunity to shape the future of chip design and impact our engineers who develop the next generation of our products! You will lead a high-impact team that develops software solutions used by thousands of RTL design and integration engineers globally across all chip families (iPhone, iPad, Mac, Apple Watch, and more).
In this role, you will be a key catalyst in transforming front-end hardware design into a modern, agile discipline. You will spearhead the transition to agentic workflows-redefining how RTL and integration teams operate in the AI era. This role combines deep knowledge of RTL/FE flows with modern software engineering practices, people leadership, and a transformative vision for engineering methodology.

Responsibilities
People Leadership: Lead, mentor, and grow a team of ~20 CAD engineers, driving talent acquisition, technical mentorship, performance management, and career development.
Agentic Flow & Methodology Transformation: Drive the team and broader RTL/FE community toward agentic workflows. Act as an organizational change agent, pioneering modern, agile methodologies that transform daily design and integration practices.
LLM Harness & Agentic Tooling: Own the architecture and execution of the LLM harness for RTL/FE flows (e.g., autonomous violation triage for Lint/CDC/RDC, intelligent connectivity synthesis, and design assist agents). Establish rigorous benchmarks to continually evaluate and elevate workflow accuracy and autonomy.
RTL Integration & Connectivity Tooling: Own end-to-end RTL integration tools, including connectivity generation, SoC assembly automation, IP packaging, and structural checks.
Static Sign-off Checks: Drive methodology, deployment, waiver governance, and sign-off metrics for Lint, CDC, RDC, and related static verification domains.
Roadmap & Milestone Alignment: Define strategic roadmaps and near-term execution plans aligned with multi-project tapeout milestones and long-term organizational goals.
Stakeholder & EDA Vendor Partnership: Collaborate closely with RTL design and integration leads to turn evolving design challenges into robust software solutions. Partner with EDA vendors to resolve escalations and influence tool roadmaps.
Software Excellence: Champion software engineering best practices, modern Python development, scalable cloud architectures, and robust CI/CD infrastructure within CAD.