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Our Autonomous Driving group in Haifa is looking for an Electrical Validation & Embedded SW Engineer. This is an exciting opportunity to join a growing team of highly talented engineers, working on the worlds most advanced SoCs for ADAS and self-driving vehicles.
Electrical Validation engineers enable, debug, and validate high-speed interfaces - like LPDDR4/5/6, PCIe Gen4/5, CDPHY, and MPHY - using high-end Lab measurement equipment and advanced SW tools. This dynamic work environment requires interfacing with Silicon and hardware design engineers, Software developers, Signal Integrity, and System Validation teams. The proximity to Signal/Power integrity simulation activities - we are a single SIPI/EV team - is another powerful advantage, enabling joint simulation-measurement effort.
What will your job look like:
You will join a team of talented and experienced EV/SI/PI engineers with wide scope of responsibility, from Pre-Si SI/PI simulations to Post-Si Electrical validation and debug, covering all the high-speed analog interfaces of our EyeQ products.
Responsibilities include performing electrical spec compliance and system margin validation, interface optimization, statistical results analysis, validation flow definitions and automation, validation SW tools development, etc.
You will also deal with FW development, automation enabling, data post-processing and debug of high-speed interfaces, like LPDDR4/5, PCIe Gen4/5, and D/C/MPHY.

We are looking for an Algorithm Developer who will be challenged to solve real-world problems using Computer Vision and Signal Processing techniques. Our mission in the Algorithms department has a significant impact on autonomous driving technologies and on saving lives.
In this position, you will combine classic programming and algorithm development in Python and C++, and be responsible for maintaining the product and developing new features. As an Algorithm Developer, you will learn and develop new algorithms that can address new problems and challenges as they arise.
The work in our algorithms department is dynamic and involves developing algorithms from the early stages of research through to production, while collaborating with other teams throughout the organization.
What will your job look like:
Your job will include a combination of classic programming and algorithm development.
You will develop in both C++ and Python.
You will need to both maintain the product and develop new features.
You will need to learn and develop new algorithms that can address new problems as they arise.

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.

As a formal verification technical lead you'll work to identify targets and complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.).

Responsibilities
You will be responsible for: Working with our world-classP design engineers to develop a formal micro-architecture specification. Formalizing the refinement from architecture to micro-architecture. Developing comprehensive formal verification test plan. Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture. Crafting novel and creative solutions for verifying complex design micro-architectures. Developing and implementing re-usable and optimized formal models and verification code base. Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.

As a member of our ML group, you will research and build AI systems that change how our silicon is designed. Many of these problems are still open: the right way to frame the problem isn't known yet, and the data is scarce or noisy.

We are looking for a strong researcher who enjoys working closely with design teams to turn open-ended questions into well-posed research problems, and who wants to see the results used in real projects. Success in this role means models and agents that measurably improve designed chip metrics (Power, Performance, and Area) and design turnaround. You will join a growing team of AI and software engineers working with our chip design teams.

Responsibilities
Research and develop AI methods for the physical design flow, from floorplanning and placement through routing and timing closure, combining predictive models, optimization, and generative AI.
Design and build agentic workflows that connect LLMs to EDA tools, design data, and internal infrastructure, to automate and speed up tasks such as flow setup, debug, design exploration, and analysis.
Work with design teams to turn open-ended problems into well-defined research questions with clear metrics, baselines, and success criteria.
Develop robust AI methods for limited, noisy, or imbalanced data, leveraging domain knowledge and advanced learning techniques.
Own data end to end: extract useful signal from EDA tool outputs and design databases, validate and clean it, and build datasets and benchmarks where none exist.
Run careful experiments and evaluations for both models and agents, and report clearly what works and what doesn't.
Work with software engineers and design teams to bring promising prototypes into production flows, and improve them based on feedback from real projects.
Help shape new research directions as our work grows, follow the AI and EDA literature, and bring relevant ideas to the team.

We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.


You will be responsible for:
Develop/support automated block and full chip level signoff flows.
Full Chip Timing/Noise convergence and full signoff for high quality TO
Enable hierarchical Timing flows.
Power optimizations.
Generate block level budget and context for correlation with Full Chip.
Drive custom IP integration and custom timing checks flows.
Close work with Design, DFT, architecture and Power team.

As a manager in the RTL/FE CAD team, you have the opportunity to shape the future of chip design and impact our engineers who develop the next generation of our products! You will lead a high-impact team that develops software solutions used by thousands of RTL design and integration engineers globally across all chip families (iPhone, iPad, Mac, Apple Watch, and more).
In this role, you will be a key catalyst in transforming front-end hardware design into a modern, agile discipline. You will spearhead the transition to agentic workflows-redefining how RTL and integration teams operate in the AI era. This role combines deep knowledge of RTL/FE flows with modern software engineering practices, people leadership, and a transformative vision for engineering methodology.

Responsibilities
People Leadership: Lead, mentor, and grow a team of ~20 CAD engineers, driving talent acquisition, technical mentorship, performance management, and career development.
Agentic Flow & Methodology Transformation: Drive the team and broader RTL/FE community toward agentic workflows. Act as an organizational change agent, pioneering modern, agile methodologies that transform daily design and integration practices.
LLM Harness & Agentic Tooling: Own the architecture and execution of the LLM harness for RTL/FE flows (e.g., autonomous violation triage for Lint/CDC/RDC, intelligent connectivity synthesis, and design assist agents). Establish rigorous benchmarks to continually evaluate and elevate workflow accuracy and autonomy.
RTL Integration & Connectivity Tooling: Own end-to-end RTL integration tools, including connectivity generation, SoC assembly automation, IP packaging, and structural checks.
Static Sign-off Checks: Drive methodology, deployment, waiver governance, and sign-off metrics for Lint, CDC, RDC, and related static verification domains.
Roadmap & Milestone Alignment: Define strategic roadmaps and near-term execution plans aligned with multi-project tapeout milestones and long-term organizational goals.
Stakeholder & EDA Vendor Partnership: Collaborate closely with RTL design and integration leads to turn evolving design challenges into robust software solutions. Partner with EDA vendors to resolve escalations and influence tool roadmaps.
Software Excellence: Champion software engineering best practices, modern Python development, scalable cloud architectures, and robust CI/CD infrastructure within CAD.

We are seeking an experienced Signal/Image Processing and Machine Learning engineer to join our team. The role focuses on developing innovative, real-time deep learning and signal processing solutions for new sensing and imaging systems, including video restoration. You will be part of an interdisciplinary team developing technologies that will shape future Apple products.
Description
Algorithm and model development:
- Design, implement, and optimize signal processing and machine learning models for sensing and imaging tasks, including video restoration.
- Develop and validate models using real sensor data, simulated data, and public datasets.
- Prepare, filter, process, and analyze large-scale datasets to train and evaluate models.
- Analyze your algorithm's results and benchmark them against leading methods, and theoretical bounds.
- Optimize models for real-time performance, low latency, and resource efficiency on-device.

Sensing and research:
- Develop algorithms that combine classical signal processing with learned models to extract robust information from sensor data.
- Investigate efficient architecture patterns (lightweight backbones, attention mechanisms, recurrent designs) suitable for real-time, on-device inference.
- Explore how algorithmic approaches can mitigate artifacts and limitations of new sensing and imaging systems.
- Stay current with recent advances in signal processing, computer vision, and machine learning.

Collaboration and technical leadership:
- Work closely with ML researchers, SW, HW, sensor, and architecture engineers to translate research ideas into robust models and practical, shipping systems.
- Provide technical guidance and mentorship to junior engineers, and help shape the team's technical direction.

Responsibilities
- Own the end-to-end development of real-time algorithms, from concept and prototyping through validation and deployment.
- Define evaluation methodology, metrics, and failure analysis processes for sensing and imaging algorithms.
- Drive trade-off decisions among accuracy, latency, power, and memory across algorithm, HW, and system constraints.

We are seeking an experienced Signal/Image Processing and Machine Learning engineer to join our team. The role focuses on developing innovative, real-time deep learning and signal processing solutions for new sensing and imaging systems, including video restoration. You will be part of an interdisciplinary team developing technologies that will shape future Apple products.
Description
Algorithm and model development:
- Design, implement, and optimize signal processing and machine learning models for sensing and imaging tasks, including video restoration.
- Develop and validate models using real sensor data, simulated data, and public datasets.
- Prepare, filter, process, and analyze large-scale datasets to train and evaluate models.
- Analyze your algorithm's results and benchmark them against leading methods, and theoretical bounds.
- Optimize models for real-time performance, low latency, and resource efficiency on-device.

Sensing and research:
- Develop algorithms that combine classical signal processing with learned models to extract robust information from sensor data.
- Investigate efficient architecture patterns (lightweight backbones, attention mechanisms, recurrent designs) suitable for real-time, on-device inference.
- Explore how algorithmic approaches can mitigate artifacts and limitations of new sensing and imaging systems.
- Stay current with recent advances in signal processing, computer vision, and machine learning.

Collaboration and technical leadership:
- Work closely with ML researchers, SW, HW, sensor, and architecture engineers to translate research ideas into robust models and practical, shipping systems.
- Provide technical guidance and mentorship to junior engineers, and help shape the team's technical direction.

Responsibilities
- Own the end-to-end development of real-time algorithms, from concept and prototyping through validation and deployment.
- Define evaluation methodology, metrics, and failure analysis processes for sensing and imaging algorithms.
- Drive trade-off decisions among accuracy, latency, power, and memory across algorithm, HW, and system constraints.

We are looking for a hands-on engineer to join our Platform Architecture post-silicon team. This team analyzes and tunes the performance and power of Apple Silicon for the Mac, and takes the learnings and measurements to drive SoC architecture change for future chips. If you work comfortably across the hardware/software stack, and the idea to bring up brand-new chips that just arrived from the fab does not scare you but gets you excited, when we would like to hear from you.

You will join a multidisciplinary team of architecture, silicon design, and system software engineers driving the performance and energy efficiency of Apple SoCs. The work spans application software, system software, SoC architecture, and microarchitecture, and sits at the intersection of measured silicon behavior and forward-looking architecture definition. You will build a deep understanding of how current and planned Apple products behave end to end, and use it to influence both hardware and software direction.

Responsibilities
Tune and define SoC memory and fabric performance state controllers on unreleased silicon, and propose improved control and observability mechanisms for future generations.
Plan and execute architecture studies that drive performance and energy-efficiency decisions for future SoCs.
Build tools, workflows, and automation for repeatable analysis of simulated and measured data, including terabyte-scale traces from prototype devices.
Architect hardware features that improve workload characterization and enable robust online control of power and performance.
Debug complex interactions between system software and SoC hardware.
Assess the feasibility of future use cases, SoCs, and products.
Communicate findings across chip design, architecture, software, and system teams to enable data-driven decisions.