לוח משרות דרושים מהנדסים בגבעתיים

Requirements:
Strong technical skills
Quick learner
Independent
Good communications skills
Knowledge in advanced verification methodologies (specman, system Verilog) - an advantage
Required Education:
BSEE/MSEE.

Requirements:
Youll do it using:
3+ years of experience in automation development, with a focus on Server side (Python)
Bachelor's degree in Computer Science, Engineering, or related discipline
Experience with AWS, docker, Jenkins, Git
Knowledge of Linux environments
Proficiency in English
Advantage:
Experience with performance/load tests
Background in mathematics/statistics
Youll excel by:
Demonstrating strong analytical and problem-solving skills
Being an independent team player, fast learner, and get-things-done person
Having excellent communication skills
Having a can-do approach
Being resourceful and creative.

Requirements:
Youll Do It Using:
7+ years of backend engineering experience, including 2+ years in a leadership role, with a hands-on background that informs architectural decisions, complex design reviews, and engineering mentorship that drives high-quality delivery.
Deep expertise in microservices architecture, distributed systems, and cloud-native design on platforms such as AWS, GCP, or Azure using Kubernetes and Helm- with a proven ability to build scalable, resilient, and maintainable systems at scale.
Strong command of observability practices, including hands-on experience with tools such as Prometheus, Grafana, or Splunk to implement monitoring, distributed tracing, alerting, and full operational visibility.
Solid experience with data and messaging technologies, including SQL/NoSQL databases, caching layers and message brokers such as PostgreSQL, Redis, Kafka, RabbitMQ, and Elasticsearch.
Proficiency in Python for building scalable backend services, with a focus on clean, production-grade code and seamless integration of AI components.
Hands-on experience with Generative AI, including LLMs, RAG pipelines, embeddings, and agent frameworks, paired with familiarity across AI tooling ecosystems such as AWS Bedrock, LangChain, LangGraph, OpenAI APIs, and vector databases.
Fluency in agile methodologies and delivery tooling such as Jira to manage team workflows and consistently ship high-quality software in fast-moving environments.
Advantages:
Familiarity with Machine Learning or Data Science concepts, enabling better collaboration with AI-focused teams.
Prior experience in AI/ML infrastructure, MLOps, or agent orchestration.
Exposure to data engineering, security, or AI ethics considerations in product development
Youll Excel By
Demonstrating exceptional leadership and communication skills, inspiring and organizing teams to achieve ambitious goals.
Thinking strategically and acting decisively, balancing technical depth with business priorities to deliver impactful solutions.
Fostering collaboration and trust, building strong relationships across product, engineering, and data science teams.

Requirements:
Youll do it using:
3+ years of Proven experience in manual QA testing for complex systems
Deep understanding of infrastructure testing methodologies
Familiarity with testing integrations with third-party services and APIs by using Postman, Swagger, or similar tools
Strong understanding of QA processes, test case design, and defect tracking tools
English proficiency (written and verbal)
Background in test automation using Python
Background with relational databases and SQL
Experience working with Jira
Proven ability to break down requirements into scenarios
Strong understanding of software testing methodologies (functional, regression, API, performance, and scalability)
Background with cloude bases applications - an advantage
Knowledge of performance testing and monitoring tools - an advantage
Experience in the insurance or banking industries - an advantage
Ability to interpret logs and identify essential information - an advantage
Youll Excel By:
Strong analytical skills and attention to detail
Owning the quality of core components.
Excellent collaboration and communication skills, working effectively with cross-functionalteams.
Identifying gaps early and proactively improving testing strategies.
Thriving in a fast-paced environment, managing multiple priorities effectively.

Requirements:
Youll do it using:
3+ years of Proven experience in manual QA testing for complex systems
Deep understanding of infrastructure testing methodologies
Familiarity with testing integrations with third-party services and APIs by using Postman, Swagger, or similar tools
Strong understanding of QA processes, test case design, and defect tracking tools
English proficiency (written and verbal)
Background in test automation using Python
Background with relational databases and SQL
Background with cloude bases applications - an advantage
Knowledge of performance testing and monitoring tools - an advantage
Experience in the insurance or banking industries - an advantage
Youll Excel By:
Strong analytical skills and attention to detail
Owning the quality of core components.
Excellent collaboration and communication skills, working effectively with cross-functional teams.
Identifying gaps early and proactively improving testing strategies.
Thriving in a fast-paced environment, managing multiple priorities effectively.

Requirements:
B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or equivalent
At least 3 years of experience in implementing PCIe initialization code and PCIe subsystem, PHYs training, and calibration software.
Experience in Physical Layer (PHY) design and debug.
Experience in HW-SW integrations.
Strong debugging skills using high-end lab equipment (Analizer, Scope, BERT)
Experience in Silicon power-on - advantage
Strong knowledge of Python, C and C++ - advantage

Requirements:
B.Sc. or higher degree in Electrical Engineering from a leading institution
3+ years experience in building emulation models, running tests on emulation machines, and debugging issues within the time constrictions of silicon design projects while handling multiple priorities
Experience with emulation platforms such as Palladium, Veloce, or Zebu, including compilation, debug, power, performance, and throughput tuning.
Familiarity with Linux environments
Experience with languages such as : C, C++, Perl, Ruby, System Verilog, Verilog, Make
Familiarity with interfaces such as PCIe, SPI, UART, ETH: advantage
Familiarity with embedded systems: advantage
Knowledge of FPGA: advantage

Requirements:
7+ years of physical design experience, working on complex subsystems
Experience in leading BE projects, subsystems and or complex high speed blocks
Experience in leading people (technical and or managerial )
Experience working in advanced node implementation flows
Good Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, CTS, place and route.
Good understanding and experience in physical design verification methodology for debugging LVS and DRC issues at chip and block level
Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power
Working knowledge of extraction and STA methodologies and tools
Good capabilities of scripting languages, such as Perl, Python and Tcl

Requirements:
7+ years of physical design experience
At least 2 years in technical leadership and/or people management roles.
Proficient in EDA tools such as Synopsys, Cadence, and Mentor for physical design tasks such as floor planning, placement, clock tree synthesis (CTS), routing, and timing analysis.
Expertise in timing closure, power analysis, and optimization methodologies.
Strong understanding of physical verification concepts, including DRC (design rule checking), LVS (layout versus schematic), and sign-off procedures.
Excellent team player with strong mentorship and management skills.
Demonstrated problem-solving capabilities and ability to thrive in a fast-paced, collaborative environment.
Effective verbal and written communication skills to interface with cross-functional teams and provide technical guidance.

Requirements:
6+ years of experience in complex ASIC designs
VLSI expert with a deep understanding of chip architecture and design flows
Excellent interpersonal skills, able to drive colleagues to achieve the project goals
Experience in design for timing and power
Experience working with various front-end tools and flows (CDC, LINT, Synthesis, etc)
Experience in high frequency or CPU design - an advantage

Requirements:
7+ years of physical design experience, leading complex process designs
In-depth knowledge of process and circuit design
Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, CTS, place and route
Experience developing and implementing power-grid and clock specifications
Good command of industry-standard physical design and synthesis tools
Understanding of scripting languages, such as Perl and Tcl
Working knowledge of extraction and STA methodologies and tools
Good understanding of physical design verification methodology for debugging LVS and DRC issues at chip and block level
Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power
Leading projects and managing small groups: advantage

Requirements:
BSc/MSc in Electrical Engineering/Computer Science.
8+ years of experience in VLSI backend (RTL2GDS).
5+ years experience in STA (Prime-Time/Signoff).
Experience Full chip STA on complex SoCs experience.
Expert knowledge and hands-on experience in timing closure & signoff methodologies.
Good knowledge of DFT architecture and DFT timing related issues
Good knowledge of Async timing concepts & verification.
Good knowledge of the full backend flows from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration, high-frequency designs)

Requirements:
6+ years of verification experience, including hands-on experience building complex environments from scratch
Advanced knowledge of verification flow, SOC architecture and design
Expertise in verification languages such as SystemVerilog, UVM, Spaceman
Knowledge of industry standard tools, including Verilog, Verilog simulator, and debug
Clear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophy
Bachelor degree in electrical engineering or computer science, or equivalent experience

Requirements:
MSc/BSc in Computer Science or other equivalent educational experience.
3-5 years of advanced C++ experience, with excellent coding skills.
Deep understanding of the internals of operating systems, IPC, and multi-threaded programming
Familiarity with device and memory management in operating systems
Experience in Linux kernel development
Ability to work in a multi-task and dynamic environment
Excellent communication and teamwork skills
Strong problem-solving skills and the ability to analyze and debug complex issues.
Advantage - Familiarity with and passion for any of the following - machine learning, compilers, parallel programming, high-performance and massively parallel systems, processor and computer architecture

Requirements:
5+ years of experience in AI/ML engineering, performance optimization, or ML systems.
Deep understanding of LLM architectures, training & inference mechanics, and modern ML frameworks.
Strong proficiency in PyTorch ecosystem, with a specific focus on performance tuning via Triton, Cuda or MLIR-based compiler frameworks.
Hands-on expertise profiling and optimizing kernels (GEMM, attention, softmax, token pipelines).
Demonstrated experience running or tuning MLPerf or similar large-scale benchmarks.
Strong Python and C++ development skills.
Proven leadership experience: mentoring, guiding, or managing engineers.