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Requirements:
5+ years of experience in high-speed SERDES design, implementation, or research, with hands-on involvement in previous generations of Ethernet standards (e.g., 100G, 200G, 400G).
Proven experience with IEEE 802.3 working groups and standards, particularly in areas related to Ethernet and optical PHY layer technologies (e.g., 802.3ba, 802.3bs, 802.3cd, 802.3ck)
Deep knowledge of modulation techniques such as PAM4 and NRZ, as well as high-speed signaling protocols used in both optical and copper interconnects
Expertise in physical layer research, signal integrity, channel modeling, equalization and error correction techniques for high-speed links
Experience working with key industry players, vendors, and consortiums to shape standards and drive technology adoption
Strong ability to produce technical reports, white papers, and presentations that distill complex technical information into actionable insights
How would you stand out:
Advanced Degree: Masters or PhD in Electrical Engineering, Communications Engineering, or a related field
Expertise and knowledge in in PCS/PMA sublayers, GMII Interface and MAC (Media Access control) in IEEE 802.3.
Extensive involvement in developing Ethernet standards from 100G up to 400G, with insights into the evolution toward 800G and Terabit Ethernet
Demonstrated leadership in managing cross-functional engineering projects related to PHY layer technologies and SERDES interface innovation
Previous experience presenting at or contributing to major industry conferences and events (e.g., OFC, ECOC, IEEE Ethernet Alliance meetings).

Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Good understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store units, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory controller.
Good understanding of high speed digital VLSI design flow and methodology
Understanding of trade-offs between power, performance and area appropriately to meet the requirements of the product.
At least 6 years of experience in one of the leading CPU companies
Familiarity with the ARM\IA architecture and the micro-architecture for current ARM\IA CPU cores.
Software development (C, assembly).
Hands on experience as a Front end ASIC designer
DESIRED
Co-operate and communicate well with the architecture team and other members of the development.
Excellent verbal and written communication skills.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
MSc or BSc in computer science/EE or area related to computer architecture, or equivalent research experience in industry
At least 7 years of relevant research and development experience in industry and academia in the following areas:
Computer architectures: instruction set architecture, microarchitecture, cache sub-system, memory sub-system, NOC, interconnect
Workload characterization and analytical model generation
System Modelling and emulation of HW.
Simulation of Software workloads and Software applications on HW simulator
Ability to provide innovation and global vision throughout the company
Excellent communication, presentation and reporting skills
Experience working with highly technical teams and communicating to non-technical partners.
Excellent oral and written English.

Requirements:
Bachelors degree in electrical engineering, SW engineering or computer science.
Minimum 7 years of experience in C programming for embedded systems.
Proven experience in developing software for multi-threaded operating systems (e.g. FreeRTOS, ThreadX, Embedded Linux).
Strong debugging and problem-solving skills in embedded environments.
Strong interpersonal skills and a good team player.
Quick learner, motivated, self-driven and independent.
Advantages
Knowledge of networking stack and protocols TCP, UDP, HTTP, etc.
Familiar with LTE.
Experience with Python for testing, analysis, and other applications.

Requirements:
BSc with excellence in Electrical/Computer Engineering
At least 3 years of experience in ASIC design
Experience in SoC design - advantage
Background in processor architecture, wireless communication protocols, very low power design - advantage
Experience in system performance and power analysis - advantage
Knowledge in Verilog, Specman, and scripting languages - advantage
Personal skills
Thinker, team player and motivated
Multi-disciplinary, self-learner, curious engineer