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We are looking for a Formal Verification Engineer for our Networking team!
This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.
Learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.

We are looking for a Formal Verification Engineer for our Networking team!
This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.
Learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.

We are looking for a dedicated SoC Clocks Design Automation Engineer to join our Networking Silicon team. In this role, youll focus on developing and supporting clock-related design flows and methodologies for SoC and networking chips, ensuring efficient and high-quality design implementation. Youll also chip in to SoC top-level automation and integration activities, building on existing flow infrastructure to improve efficiency and consistency across projects. Introduction
What you'll be doing:
Develop and maintain design automation and methodologies for SoC and networking clock flows.
Collaborate with design, STA, and project teams to ensure timely and high-quality design closure.
Develop and improve SoC top-level automation scripts and flows built upon existing infrastructure and tools.
Support SoC integration and construction flow activities across multiple projects.
Assist in timing, power, and noise analysis to ensure efficient performance.

We are looking for a Senior QA Software Engineer who combines network protocol expertise with strong Python automation skills. Does debugging a BGP EVPN route leak excite you as much as refactoring a test framework? Then we should talk!
What you'll be doing:
We don't just complete checklists; we collaborate closely with R&D to lead the quality of new features from design to deployment. In this role, we:
Review architectural designs and requirements for new features introduced to the product
Drive the design, development, and execution of tests across functional, performance, and security scopes as part of SW GA and update releases
Develop Python automation suites built on clean OOP principles
Chase down defects and validate fixes until we fully resolve the root cause
Leverage the SimX platform to validate code and debug the ASIC long before hardware arrives .

We are looking for Host Management Architect to working on an innovative data-center management and security. Leading the SW/FW/HW solution addressing the technology of managing servers in a data center.
What you will be doing:
Define the next generation technologies, products and solutions to address management and product security.
Defining the architecture of the FW, SW and HW and supporting R&D teams throughout the development process.
Become an expert in host management technologies and serve as the technical reference for our R&D teams.
The role requires working with customers, understanding their requirements and painful points and translating it into product features.
The architect will join the host management team.

Required Senior Package Layout Engineer
Our Networking unit has continuously reinvented itself over two decades. Our high-speed products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions. We're looking to grow our company and build our teams with smart people who can join us at the forefront of technological advancement. Our IC Packaging design team is looking for a Senior IC Packaging Design Engineer to join our package team. and focus on delivering and designing state of the art high-speed Interconnect systems for Supercomputers and Datacenters. This position will collaborate with Technical Package Lead and cooperation with different design teams and development of complex, detailed layout of IC substrates for our products.
What you'll be doing:
As part of a IC Packaging design team, you will collaborate to implement high speed and PDN design for ASIC packages.
Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.
Optimize package pin out incorporating system level trade-offs of pins assignment.
Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.
In close co-operation with the SI/PI/HW design teams and product teams
Planning, ensuring stakeholder management and leading projects from start to finish.

We are looking for a Software Engineer to join its Software R&D Linux kernel team, located in Yokneam. The position would be part of a team that implements and maintains sophisticated drivers and userspace libraries for groundbreaking network technologies.
What youll be doing:
You will craft and implement kernel drivers for our state or art network devices as well as userspace libraries.
Collaborate and debug with teams across the globe to provide the best solutions for our customers.
Develop high-quality code for Linux kernel and other open-source environments.
Work in a Continuous Deployment environment of fast development/deployment cycles.
Be a part of an experienced team with a great atmosphere.

Required Senior Hardware Architect, Deep Learning GPU and System
We push the boundaries of Artificial Intelligence using Deep Learning every day, designing better algorithms, hardware and software. By joining the Compute Deep Learning Architecture team you would be in an outstanding position to influence all three and help us push the boundaries even farther in large number of fields like datacenters and autonomous machines. We are looking for remarkable candidate passionate about AI and Deep Learning as much as we are. Would you like to make a difference?
What you'll be doing:
As a member of our Hardware architecture deep learning team, you will contribute to features that help next-generation GPUs and systems advance the state of AI.
This position requires you to collaborate with other hardware and software engineers as well as DL researchers.
Your day to day work will include analyzing the behavior of various deep learning methods on current and future hardware architectures and propose new features to accelerate it. The features could be HW, SW or Algorithmic - usually combining all.
The main focus of this job is from hardware architecture perspective and workload performance.

Our Networking division is looking for an excellent System Product Engineer! Our Networking division is a leading supplier of innovative end-to-end InfiniBand and Ethernet connectivity solutions and services for servers and storage. We offer market-leading solutions that include adapter cards, switches, cables and software to support networking technologies. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. In addition, we serve a wide range of markets including high performance computing, enterprise, data centers, cloud computing, big data and Web 2.0. We are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry.
The System product engineer is responsible for stabilizing hardware products from the first build unit through ramp-up and transition to high-volume mass production. This role plays a critical part in ensuring product quality, yield, and test robustness for our cutting-edge platforms by leading debug infrastructure development, systematic failure analysis, and data-driven continuous improvement across the NPI lifecycle.
What you'll be doing:
Own end-to-end product stabilization from first article to production release.
Develop and maintain hardware debug infrastructures, tools, and methodologies to support efficient root cause analysis.
Monitor, analyze, and improve yield performance during NPI.
Perform deep-dive failure analysis and root cause investigations to improve product robustness, quality, and throughput.
Improve test stability, coverage, and repeatability while reducing false failures.
Collaborate closely with Mechanical NPI engineers, Test Development teams, R&D, and manufacturing partners.
Apply data analysis techniques to identify systemic issues, trends, and optimization opportunities.

We are looking for a Formal Verification Engineer for our Networking team!
This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking Switch technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our Switch team delivers world class Bridge and router solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver smart and high bandwidth multi port switches. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.
You will work on developing new formal verification methodologies and tactics.

We are seeking an experienced second-line engineering manager to lead the Validation group - a multi-disciplinary team of engineers and first-line managers responsible for end-to-end validation of production line Functional Tests (FT), Customization Tests, automatic production JIGs, test boards (TBs), and all tester-related electronics. The successful candidate will own the groups strategy, execution, and people development while operating in a fast-paced, multi-product environment.
What Youll Be Doing:
Define and drive a strategic roadmap for the group, including automation, tooling, methodologies, and scaling strategies
Establish and evolve validation methodologies and standards (JIG V&V, test board validation, regression analysis, Cp/Cpk, production coverage metrics) across all product families
Drive continuous improvement initiatives in validation quality, cycle time, first-pass yield (FPY), and test time reduction (TTR)
Identify and champion automation and AI-driven approaches to validation workflows
Own end-to-end V&V execution across NPI (New Product Introduction) and Mass Production phases for NICs, DPUs, and Switches
Drive the V&V matrix methodology across 30+ NIC projects (FT + Customization) and 20+ Switch projects simultaneously
Lead, mentor, and develop first-line managers - empowering them to independently manage their sub-teams while maintaining alignment with group strategy.

Our Networking Software and System Architecture is looking for a Senior Technical Program Manager to lead and scale execution governance across our architecture initiatives. This role owns end-to-end program governance for Networking Software Architecture programs, from intake and solution exploration through architecture commit and engineering handoff. You will operate at the intersection of Architecture, Product Management, and Engineering, ensuring structured, measurable, and predictable execution aligned to our Product Lifecycle framework.
What you'll be doing:
Lead end-to-end governance of Networking Software Architecture initiatives from intake through architecture commit and engineering POR handoff
Drive structured execution aligned to our PLC process, ensuring clear gate criteria, ownership, and decision accountability
Formalize research and exploration programs into measurable architecture deliverables with defined scope, trade-offs, and success criteria
Establish and maintain a single authoritative view of scope, priorities, risks, dependencies, and KPIs across initiatives
Manage complex cross-domain dependencies across Switch, Host, E2E, Platform, and external stakeholders
Partner closely with Product Management and Engineering to ensure predictable, disciplined transition into POR execution
Define and operationalize architecture KPIs and dashboards to provide leadership-level visibility and data-driven insights
Drive governance forums including intake reviews, architecture commit reviews, and ongoing risk and status reviews
Leverage and standardize program management tooling including JIRA, Redmine, Confluence, and controlled documentation repositories
Proactively identify execution risks and drive structured mitigation and escalation when required.