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You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

As a Technical Leader, you will be at the forefront of advancing Tetragons capabilities. You will guide architectural direction while staying deeply engaged in building the systems that power our platform. Your impact will span designing high-performance data pipelines, optimizing database and distributed system performance, and ensuring massive streams of system events can be ingested, aggregated, and distilled into meaningful intelligence.

You will collaborate closely with teams across Cisco, including Hypershield and Splunk, to create the integration points that transform raw data into actionable insights for enterprise security. In this role, youll solve some of the most complex system-level challenges in observability and infrastructure, helping Tetragon evolve to meet the needs of modern cloud-native environments.





What youll do:

Develop high-quality Go (and eBPF) code for the Tetragon project.

Design and implement new Tetragon features to enhance its capabilities for Runtime security detection and enforcement

Design and optimize systems for large-scale Tetragon deployment and operation in K8s or VM platforms

Architect infrastructure that converts raw event data into intelligence streams with minimal performance overhead.

Contribute to open-source projects and represent Cisco Isovalent in community discussions.

Participate in architecture reviews, code reviews, and documentation.

The Design for Test (DFT) team is part of the design group, which focuses on logic design, RTL development, and running verification tests.

Their main role is to design test structures embedded within the chip to ensure proper functionality after manufacturing.

The goal is to detect potential manufacturing defects with maximum efficiency and filter out faulty units before they reach the market.



What You'll Do

Insert DFT logic, perform synthesis, and run Automatic Test Pattern Generation (ATPG) to ensure hardware testability.

Execute Gate Level Simulations, timing checks, and DRC checks to maintain rigorous design integrity and performance standards.

Run regressions and perform deep-dive debugging on simulation failures as part of the core verification process.

Work in a small, agile team with an intimate atmosphere that offers direct mentoring and broad professional growth.

As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

we are looking for a ASIC Engineer
Your Impact
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab

Tetragon Threat Detection Engineers primarily focus on creating and maintaining

Tetragon runtime security policies, based on the latest threat intelligence, vulnerability disclosures, and their own research.

Policies can act either as a mitigation to known vulnerabilities or as monitoring and protection against unknown security issues.

What youll do:

Develop and maintain Tetragon runtime security policies to ensure customers have good visibility of suspicious activity on their infrastructure and are protected against the latest emerging threats

Help design frameworks and architectures that allow customers to easily consume policies and understand their overall security posture

Monitor vulnerability disclosures (CVEs) and the latest threat intelligence to develop Tetragon runtime security policies

Work with software engineers at Isovalent and Cisco to improve and enhance the capabilities of Tetragon security policies

Interact with solution architects and customers as necessary to support and deploy Tetragon security policies in production

Publish content and give talks based on your work

Join a platform engineering team and provide hands-on technical leadership in evolving a Kubernetes-based platform for enterprise network applications, shaping how applications integrate with and operate across cloud, hybrid, edge, and customer-managed environments.

Define platform architecture, technical strategy, and multi-release roadmaps; translate product and operational needs into clear designs and implementation plans.
Design and evolve Kubernetes capabilities, including cluster lifecycle, controllers and reconciliation, custom resources, scheduling, networking, storage, service discovery, and upgrades.
Lead the design and development of shared platform services for connectivity, identity and access management, distributed data, observability, lifecycle automation, and administration.
Improve reliability and security through high-availability design, recovery, backup and restore, capacity planning, production debugging, threat modeling, and vulnerability remediation.
Prepare the platform for future AI workloads through workload isolation, resource governance, secure model serving, telemetry, and accelerator support.
Raise engineering standards through hands-on development, design and code reviews, automated testing, CI/CD, incident analysis, mentoring, and AI-assisted engineering workflows.

we are seeking a Physical Design Technical Leader.