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we are seeking a highly motivated and experienced Senior Software Engineer for a position focused on developing innovative network device monitoring and visualization solution.
Meet the Team:
This position is part of Silicon One organization, based in Israel. Silicon One is the foundation of industry-leading networking hardware products, pushing the boundaries of technology and driving the next generation of high-performance, scalable solutions.
Your Impact:
Design and develop visualization capabilities within our SDK environment
Lead the development of a brand-new comprehensive self-monitoring system for network devices from the ground up
Implement a comprehensive model for capturing and managing network state information
Drive cross-team collaboration and technical strategy
Work closely with senior technical leadership
Create and refine technical requirements and system designs
Build new systems and frameworks from the ground up

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the DFT team.
This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.

we are looking for a Physical Design Manager.
You'll be part of the Cisco Silicon One team, which is at the heart of Ciscos software and ASIC design efforts.
As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Join the PHY system team, a pivotal part of silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We are looking for a Senior Algorithm Developer with experience in NLP and LLMs, who is highly motivated, collaborative, and results-driven individual who can work both independently and as part of a multidisciplinary team. The ideal candidate has a strong can-do attitude, excellent problem-solving skills, and a passion for leveraging AI to solve meaningful challenges in text analysis in the medical domain.

As part of the AI team you will:

Design, develop, implement, and evaluate robust, scalable AI algorithms and agentic workflows tailored to real-world challenges in clinical settings.

Prepare, process, and analyze complex medical data to support algorithm development and validation.

Ensure the reliability, performance, and accuracy of algorithms in production, including troubleshooting, testing, monitoring, and continuous improvement.

Collaborate closely with Product Managers and Clinical Specialists to translate clinical and business needs into data-driven solutions.

Research, develop and integrate cutting-edge text based alogirthms on medical text.

Apply NLP and Large Language Models (LLMs) to extract insights from medical texts and develop intelligent agents for optimized clinical decision support.

Stay up to date with cutting-edge advancements in GenAI, LLMs, and Deep Learning.

Organize and actively participate in seminars, book clubs, and conferences.

Main Technical Stack:

NLP/LLMs: Pydantic, Hugging Face Transformers, spaCy, Amazon Bedrock

Infrastructure: AWS, Docker

Programming Languages: Python

Deep Learning Frameworks: TensorFlow, Keras, Pytorch

we are looking for a ASIC Leader.
Your Impact:
Review micro-architecture specifications
Supervise verification team members and provide professional guidanc
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab

Youll be joining the post silicon validation team in PHY system group as part of the silicon development .
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

In this role, you will provide technical support to customers, troubleshoot networking and communication solutions, and collaborate with Engineering and Product Management to resolve technical issues efficiently.

You will also deliver professional services and support customers both remotely and on-site.

This is a full-time position with the option of working from home one day a week.

Location: Tel Aviv office Ramat-Hachayal.

Key Responsibilities
Serve as the primary technical contact for assigned customer support cases via phone, email, and web.
Troubleshoot and resolve network configuration issues, equipment faults, and product-related problems.
Analyse customer network environments to identify root causes and recommend effective solutions.
Collaborate with Engineering, Product Management, and Tier-3 Support teams to resolve complex technical issues.
Deliver Professional Services, including product implementation, configuration, technical trainings, technical consulting, etc
Provide on-site installation, troubleshooting, and technical support when required.
Maintain high levels of customer satisfaction by delivering timely, professional, and effective technical support.

We are looking for a motivated and detail-oriented Safety Laboratory Technician to join our Hardware Department lab team at our Tel- Aviv office.

The successful candidate will perform safety testing of company products in accordance with international safety standards. Comprehensive professional training will be provided as part of the role.

Key Responsibilities
Perform safety testing of company products in accordance with international safety standards.
Operate laboratory test and measurement equipment.
Set up, execute, and document safety test procedures.
Prepare clear and accurate test reports.
Maintain laboratory equipment and ensure compliance with laboratory procedures.
Work closely with engineering and regulatory teams to support product certification activities.

As a QA Engineer , you will play a key role in validating and improving our products, ensuring high quality.
You will join RADs family, as part of our team in Beer-Sheva, collaborating closely with software development teams in an agile and dynamic environment.

Location: Beer Sheva. Hybrid option once a week.

Responsibilities
Design and execute test plans and test cases based on system requirements
Identify, investigate, and report software bugs, while tracking them through resolution
Create and maintain clear test ation and reports
Collaborate with R&D teams to provide QA input throughout the development lifecycle
Communicate risks and quality concerns that may impact future releases

We are looking for a versatile Senior Software R&D Engineer and a dedicated team member to join our multidisciplinary group. This role places a heavy emphasis on hardware bring-up, low-level software development, and collaborative engineering. You will be a core player in a tight-knit team, moving seamlessly between different phases of system creation-from architecting board support packages (BSPs) and troubleshooting new hardware boards to designing high-performance application features.

Location: Ramat Hachayal, Tel Aviv. Hybrid option once a week.



Responsibilities:
Active Team Member: Collaborate daily within a diverse R&D team. Brainstorm solutions, conduct peer code reviews, and share knowledge to elevate the teams capabilities.
Hardware Bring-up & BSP: Lead the software-side bring-up of next-generation hardware. Design, develop, and debug Board Support Packages (BSPs) to seamlessly bridge the hardware-software boundary.
HW/SW Integration: Partner closely with hardware engineers to diagnose system-level bottlenecks, read schematics, and ensure optimal hardware performance.
Real-Time Feature Implementation: Design and develop high-performance software features and real-time application layers for our flagship product.
Product Implementation Design: Translate complex product requirements into scalable, highly reliable software designs and system architecture.

we are looking for a ASIC Design Engineering Technical Leader.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macro and cluster-level blocks, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsys and Cadence.
* Engaged in defining implementation and signoff methodologies.