As a Performance Software Engineer, you will be instrumental in building the core computation software that runs on custom AI accelerators. Your work will bridge the gap between host systems and proprietary hardware, encompassing everything from a custom on-board kernels to the sophisticated tooling required for real-time debugging. You will be a key player in chip bring-up and the long-term development of high-performance computation primitives and kernels, ensuring our architecture operates with maximum efficiency and deterministic performance.
Responsibilities
Develop and optimize low-level software primitives in C/C++, assembly, and architecture-specific intrinsics, primarily for RISC-V and ARM platforms.
Implement performance-critical kernels, runtime components, hardware abstraction layers, drivers, and firmware operating in bare-metal or highly constrained environments.
Work closely with hardware architects and RTL/design teams to define and validate hardware-software interfaces, memory maps, register interfaces, interrupts, synchronization mechanisms, and boot flows.
Analyze and optimize software for latency, throughput, memory footprint, instruction count, and efficient use of processor and accelerator features.
Bring up and debug software on simulation, emulation, FPGA, and silicon platforms, including low-level hardware/software integration issues.
Develop validation tests, benchmarks, and diagnostic tools for new processor, DSP, accelerator, and SoC functionality.
Contribute to architecture decisions around ISA extensions, compiler intrinsics, memory hierarchy, DMA, cache/coherency behavior, and software-visible hardware features.
Requirements: Bachelors, Masters, or PhD in Computer Science, Computer Engineering, or a related field.
Strong experience in low-level systems programming using C/C++ and assembly, with excellent understanding of how compiled software maps to machine instructions and hardware behavior.
Deep familiarity with bare-metal development, including startup code, linker scripts, memory layout, MMIO, interrupts/exceptions, timers, synchronization, and direct peripheral access.
Strong understanding of computer architecture, including pipelines, caches, memory hierarchies, virtual/physical addressing, atomics, DMA, and performance implications of different access patterns.
Hands-on experience with RISC-V and/or ARM architectures, instruction sets, calling conventions, ABI concepts, and architecture-specific intrinsics.
Experience debugging hardware/software interactions using tools such as GDB, JTAG, trace/debug interfaces, simulators, emulators, or FPGA platforms.
Ability to read hardware specifications, register descriptions, and RTL-level documentation and translate them into robust software implementations.
Strong performance-analysis and optimization skills, including profiling, disassembly inspection, compiler optimization behavior, and hand-tuned assembly where appropriate.
Language: English at a proficient level. French is a plus.
This position is open to all candidates.