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Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Good understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store units, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory controller.
Good understanding of high speed digital VLSI design flow and methodology
Understanding of trade-offs between power, performance and area appropriately to meet the requirements of the product.
At least 6 years of experience in one of the leading CPU companies
Familiarity with the ARM\IA architecture and the micro-architecture for current ARM\IA CPU cores.
Software development (C, assembly).
Hands on experience as a Front end ASIC designer
DESIRED
Co-operate and communicate well with the architecture team and other members of the development.
Excellent verbal and written communication skills.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Minimum of 10 years of proven design experience in complex processor projects.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to US, Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills
MINIMAL REQUIREMENTS
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
Ownership of the overall verification methodology for a CPU project.

Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Solid understanding of general purpose CPU micro-architecture, including load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory technologies and memory controllers.
Ability to make trade-offs between power, performance and area to meet the requirements of the product.
Hand-on experience with high power-efficient CPU on chip interconnect, coherent fabric, memory controllers.
At least 8 years experience in architecture in one of the leading CPU companies
Experience modeling microprocessors using higher-level languages, like C/C++.
DESIRED
Co-operate and communicate well with the architecture and design teams.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
Requirements:
* B.Sc. in Electrical/Electronics Engineering mandatory
* 3+ years of experience in FPGA/ASIC verification
* Hands-on experience with UVM & SystemVerilog
* Proven experience in environment integration and coverage reporting
* Strong scripting skills ( Python, TCL) Advantages:
* Experience with Assertion Based Verification (ABV)
* Familiarity with Verification IPs and communication protocols (PCIe, Ethernet, I2C, SPI, AXI)
* Background in RTL design (Verilog/VHDL).

Requirements:
* B.Sc. in Computer Science / Electrical Engineering / Computer Engineering.
* At least 3 years of development experience in a development team of complex enterprise systems.
* At least 2 years of experience in C / C ++ programming.
* Experience in multi-threading principles and programming.
* Experience in Python, JAVA, Linux, and Git.
* Great team player who knows when and how to push independently when needed.
* Strong communication skills.
Advantages:
* Experience in native mobile application development in Android or IOS.
* Experience Objective- C programming.
* Experience in NDK and JNI for Android.
* Experience with SDK development or integration. Advantages.
* Experience in reverse engineering for Android.
* Knowledge in Cyber security and Networking.
About the company:
Our mission is to protect every mobile app in the world and its users. We provide mobile brands with the only patented, centralized, data -driven Mobile Cyber Defense Automation platform. Our platform delivers rapid no-code, no-SDK mobile app security, anti-fraud, anti-malware, anti-cheat, anti-bot implementations, configuration as code ease, Threat-Events threat-aware UI / UX control, ThreatScope Mobile XDR, and Certified Secure DevSecOps Certification in one integrated system. With us, mobile Developers, cyber and fraud teams can accelerate delivery, guarantee compliance, and leverage automation to build, TEST, release, and monitor the full range of cyber, anti-fraud, and other defenses needed in mobile apps from within mobile DevOps and CI/CD pipelines. Leading financial, healthcare, m-commerce, consumer, and B2B brands use us to upgrade mobile DevSecOps and protect Android & IOS apps, mobile customers, and businesses globally. Today, our customers use our platform to secure over 50,000+ mobile apps, with protection for over 1 billion mobile end users projected.
We are an Equal Opportunity Employer. We are committed to diversity, equity, and inclusion in our workplace. We do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other characteristic protected by law. All qualified applicants will receive consideration for employment without regard to any of these characteristics.

Requirements:
* B.Sc. in Electrical Engineering from a leading university.
* Over 5 years of experience in complex ASIC verification.
* Experience in building IP verification environment.
* Experience in UVM methodology.
* Good knowledge in Verilog.
* Experience in embedded C programming – advantage.
* Good communication and interpersonal skills. SolarEdge recognizes its talented and diverse workforce as a key competitive advantage. Our business success is a reflection of the quality and skill of our people. SolarEdge is committed to seeking out and retaining the finest human talent to ensure top business growth and performance

Requirements:
* Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field
* At least 3 years of hands-on experience in FPGA development - Intel or AMD
*  Proficiency in VHDL / Verilog
* Excellent problem-solving skills and the ability to work effectively in a collaborative environment
*  Background or prior experience in Electronic Warfare (EW) systems is advantageous
* Excellent analytics problem-solving skills.

Requirements:
* A Practical engineer in mechanical/electrical engineering or equivalent is essential.
* 1-2 years of hands-on experience in R&D lab
* Experienced with measurement gauges, volt and impedance meters, as well as automated test equipment, etc.
* Experience with battery testers- An advantage
* Experienced in handling of Lithium ion batteries- An advantage
* Experience in wiring and soldering- An advantage
* Excellent communication and written skills in English is required ?SolarEdge recognizes its talented and diverse workforce as a key competitive advantage. Our business success is a reflection of the quality and skill of our people. SolarEdge is committed to seeking out and retaining the finest human talent to ensure top business growth and performance

Requirements:
Requirements:
B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Strong programming skills in Python, C/C++, TCL and SKILL, with automation scripting experience in Bash, Csh, and Perl.
Proficiency with version control systems (e.g., Git).
Excellent problem-solving and debugging abilities.
Strong communication and teamwork skills.
Ability to work independently in a dynamic, fast-paced environment.

Preffered:
Solid understanding of IC design flows across all domains (front-end, back-end, circuit, and layout).
Experience with CAD customization and enablement, including advanced tool development in Cadence Virtuoso (SKILL) and layout design automation.
Demonstrated ability to collaborate with diverse engineering teams to capture requirements and deliver robust, scalable solutions.
Hands-on experience with distributed resource management systems (SGE/UGE, LSF, Slurm) and cloud platforms (AWS, GCP, Azure) for compute infrastructure.
Familiarity with CI/CD methodologies for EDA, including regression frameworks and continuous integration practices.

Requirements:
Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
8+ years experience in full chip design.
Experience in leading the full-chip level design and successfully taping out multiple intricate SoCs.
Experience in floor planning, integration, signoff methodologies, and signoff tools for hierarchical designs.
Experience with SoC design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
Expert knowledge of the entire backend design flow from RTL to TO.
Experience with STA (Static Timing Analysis) tools like primetime or tempus.
Experience with IR drop tools like Ansys Redhawk or Volta's.
Physical Verification Expert (DRC/LVS).
Strong independent and motivated to learn quickly, hard-working, and is results oriented.
Good social skills and ability to work collaboratively with other teams.

Preferred:
Experience with high-speed serial interfaces such as PCIe, DDR, Ethernet.
Familiarity with advanced DFT flows & tools.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.

Requirements:
Requirements:
B.Sc. in Electrical Engineering or a related field.
6+ years of experience in ASIC/SoC Verification.
Experience leading verification planning and execution independently.

Preferred:
Familiarity with RDMA, Ethernet, DDR or RISC-V.

Requirements:
Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
8+ years of VLSI experience.
Experience with multi clock domain, multi power domain designs (UPF).
Methodologic approach.
Strong Motivated to learn quickly, hard-working, and is results-oriented.
Great interpersonal relations skills.

Preferred:
Networking design experience Major Advantage
Backend experience: STA tools, formal equivalence tools, frontend/backend handoff methodologies.
SoC design/Integration experience.
Proven Methodologies and Environmental Building Experience.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.

Requirements:
B.Sc. in Electrical/Computer Engineering, Computer Science, or Practical Engineering (hands-on IC layout/CAD experience also considered).
13 years of relevant industry experience or 3+ years for more senior candidates both junior and experienced engineers will be considered.
Hands on experience with layout and verification tools, including both commercial (Cadence, Synopsys, Mentor) and in-house CAD solutions.
Strong programming skills in SKILL, Python, TCL, Perl, and Shell (Csh, Bash).
Ability to debug, optimize, and troubleshoot CAD flows and layout workflows.
Familiarity with regression testing, code review, flow validation, and CI/CD practices in CAD/EDA environments.
Strong communication and teamwork skills, with the ability to work independently in a dynamic, fast-paced environment.

Requirements:
Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
47 years of experience in FPGA prototyping or emulation of ASIC/SoC designs
Strong understanding of digital design and RTL (Verilog/SystemVerilog/VHDL).
Hands-on experience with at least one emulation/prototyping platform (Palladium, Protium, Veloce, ZeBu, or FPGA-based)
Good knowledge of synthesis, timing closure, and design partitioning for FPGA/emulation.
Familiarity with verification methodologies and environments (UVM/SystemVerilog/C).
Experience with scripting (TCL, Python, Perl, or Shell) for automation.
Strong problem-solving and debugging skills.
Ability to work in a fast-paced, collaborative environment.
Excellent communication and teamwork skills.

Preferred:
Exposure to software bring-up, driver validation, or firmware testing on emulation.
Knowledge of bus protocols (Ethernet, DDR, etc.).
Experience with debug tools (waveform viewers, logic analyzers, or emulation debug frameworks).
Background in SoC architecture and hardware/software co-design.