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As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip.
Collaborate closely with Physical Design team to insure a full power integrity.
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM).
Understand root-cause analysis for voltage drop violations and EM risks.

As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a Staff DFT Engineer, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy
Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support.
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards.
​DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies.

Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production.
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance.
Drive test coverage and quality metrics to meet stringent manufacturing requirements.

Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR.
Participate in developing and maintaining cutting-edge DFT implementation flows.
Automate and improve methodologies using advanced scripting and tools.

As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Technical Program Manager, you will be the key architect of our silicons operational reality. You wont just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.

Key Responsibilities
Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.
Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.
Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.
Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.
Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.
Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.

We are seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications.
In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues.
This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed.
Key Responsibilities:
Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness.
Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions.
Develop validation tests to verify functionality, performance, stability, power, and operating margins.
Debug issues across silicon, hardware, firmware, drivers, and system software.
Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces.
Develop Python scripts and automation to improve validation coverage, regression, and test efficiency.
Analyze validation data, identify issues and trends, and drive problems to root cause and closure.
Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues.
Support the transition of new silicon from initial bring-up to a qualified, production-ready product.
Operate system platforms and laboratory equipment to support validation and debug.
Document test results, issues, root cause, and recommendations and communicate findings clearly.

As we expand our presence in Israel, we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You wont just be using tools; youll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.


Key Responsibilities
Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes.
Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows.
Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics.
Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows.