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We are a global pioneer of RADAR systems for active military protection, counter-drone applications, critical infrastructure protection, and border surveillance. We are looking for ATE software engineer As a Software Automatic TEST Equipment Engineer, you will play a vital role in developing and maintaining advanced Automatic TEST Equipment (ATE) software for electronic cards and calibration systems used in our cutting-edge Active Electronically Scanned Array (AESA) radar technology. You will collaborate closely with a multidisciplinary team to ensure the functionality, accuracy, and performance of our ATE systems. Key Responsibilities:
* ATE Software Development: Design, develop, TEST, and maintain software for Automatic TEST Equipment used in electronic card testing and AESA radar calibration.
* Integration: Collaborate with hardware engineers to integrate ATE software with testing equipment and devices, ensuring seamless operation.
* Debugging and Troubleshooting: Identify and resolve software issues, system failures, and compatibility problems to ensure optimal ATE performance.
* Documentation: Maintain accurate and up-to-date documentation.
*  Quality Assurance : Implement quality control measures to ensure that ATE software meets industry standards and complies with project requirements.
* Team Collaboration: Work closely with cross-functional teams, including hardware engineers, software developers, and project managers, to meet project milestones and objectives.
* Continuous Improvement: Stay up-to-date with industry trends and emerging technologies, and contribute to the ongoing improvement of ATE software and testing methodologies.

We are seeking a highly skilled and hands-on Radar ATE Engineer to support the end-to-end production, validation, and analysis of automotive radar systems. This role bridges automated test equipment (ATE) development and product analysis, ensuring high-quality sensor delivery and minimal downtime across global production sites. The position includes deep technical involvement in both software and hardware domains, with a strong focus on manufacturing support, system-level troubleshooting, and continuous process improvement.
What will your job look like:
Develop and maintain Automated Test Equipment (ATE) systems and debug tools to ensure robust and reliable testing of radar products.
Support high-volume Mass Production manufacturing environments by ensuring stable test operations and minimizing production downtime.
Provide ongoing support to production and test lines by addressing urgent ATE and DUT-level issues.
Develop, execute, analyze, and debug radar test sequences, automation tools, and test infrastructures using Python and MATLAB, supporting engineering investigations, production KPIs, and continuous test improvements.
Work hands-on with hardware, drivers, test equipment, and measurement instruments to support validation, production testing, and troubleshooting activities.
Collaborate closely with Software, Algorithms, RF, Hardware, Production, and System Integration teams to resolve technical issues efficiently.
Apply a strong system-level perspective to analyze and troubleshoot complex issues across software, hardware, RF, and manufacturing domains.
Perform root cause analysis, calibration, characterization, and debugging activities.
Track and manage test issues and results using JIRA and internal logging systems.
Escalate recurring, critical, or systemic failures and drive corrective actions and continuous improvement initiatives.
Monitor production performance and provide technical support to global manufacturing sites, including yield monitoring, unit status tracking, and KPI analysis.
Coordinate with Production, System Integration, and Software Engineering teams to ensure release readiness and smooth production ramp-up.

Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS.
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).

Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

Were expanding our teams and looking for an Experienced Physical Design Engineer who is ready to make a massive impact
NOTE: By applying for this position, you will have the opportunity to indicate your preferred work location: Haifa or Petach Tikva.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS .
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).

Were looking for a Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS.
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).
Signoff: on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

Our Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like:
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS.
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

We are looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting-edge technologies - Autonomous Vehicle (AV) SoC.
We know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
Develop all the necessary HW / FW / SW for the different modules.
Verify and Validate our design.
Debug and analyze coverage and yield loss.
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts - as it required by the Automotive and Safety related products market (ISO26262).

Our Unit Level Verification Team is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like:
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

We are looking for a Signal Integrity Engineer to join AV group and develop of the next generation of Autonomous Driving products.
We are a leading innovator in the automotive industry, dedicated to delivering cutting-edge technology and solutions. We are committed to advancing automotive safety, efficiency, and connectivity through our state-of-the-art ECUs.
We are seeking a highly skilled Signal and Power Integrity Simulation Engineer to join our hardware engineering team. In this role, you will be responsible for analyzing and optimizing signal and power integrity in complex electronic systems. You will work closely with design and validation teams to ensure high-performance designs that meet industry standards.
What will your job look like:
Conduct signal integrity (SI) simulations for automotive electronic systems, analyzing and optimizing high-speed interfaces, such as LPDDR4/5, PCIe Gen4/5, A/C/D-PHY, Multi Giga-Bit Ethernet .
Conduct Power integrity (PI) simulations, optimizing target impedance and AC coupling in power delivery networks to ensure optimal performance and reliability.
Collaborate with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, EDA tools vendors, and product managers to address SI/PI issues and provide actionable design recommendations.
Engage in joint simulation and measurement efforts with the Electrical Validation team to facilitate comprehensive validation of designs. Perform root cause analysis on signal and power integrity failures and propose effective corrective actions.
Generate comprehensive reports and presentations to communicate simulation findings and design strategies to technical and non-technical stakeholders.

In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.



Responsibilities:

Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.



Responsibilities:

Lead the full verification lifecycle and methodologies. Plan, Design and Execute verification of SV/UVM Block level and Full chip environments , creating and execution test plans, tracking progress, and ensuring verification closure across diverse Mix-signals SoC simulation using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

system ATE RF Engineer We are seeking a highly professional and hands-on system ATE RF Engineer to join our ATE team. In this role, you will be responsible for developing and maintaining advanced ATE (Automatic TEST Equipment) solutions for radar systems, ensuring high-performance RF calibration and testing throughout the production lifecycle.
Key Responsibilities:
* Design, develop, and implement automated Digital & RF TEST procedures and calibration tools for complex radar systems.
* Integrate hardware and software components to create robust ATE environments.
* Analyze RF performance data and troubleshoot complex system -level issues.
* Work closely with Subcontractors, ATE SW and Radar system Engineers to define and execute TEST requirements and methodologies.
* Support the transition from development to mass production, ensuring TEST reliability and efficiency.

The position is based in Netanya, with occasional travel required to the production facility in Beit She'an.