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Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems. If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role, you will:
Establish and lead a Back-End team with emphasis on RTL to GDS flow, Floorplan, Synthesis, Place and route, clock-tree, STA, layout, signoff (Timing, DRC, LVS) and Power
Be responsible for the Backend execution and methodologies
Be responsible to guide and lead contractors

Join us and be part of a company that values creativity, agility, and impactful work. Responsibilities:
* Lab tests of the analog circuits using Spectrum, Scope, and other lab equipment.
* Collaborate with software engineers to ensure seamless integration between hardware and software.

Country:
Israel

City:
Herzliya

Required Senior Formal Verification Engineer (Contractor)
Role Description
This is a full-time on-site role for a Formal Verification Engineer in Petah Tikva, Israel.
The Formal Verification Engineer will be responsible for developing and implementing formal verification environments, writing and applying verification plans, and conducting formal property verification. Additional tasks include analyzing coverage results, debugging, working with design engineers to resolve issues, and reporting outcomes to ensure the accuracy and efficiency of the designs.

Work cross-functionally with silicon, hardware, and software teams to help deliver surprise and delight in our latest products while enabling system development and stability. This role requires the technical depth and expertise to understand how things work from the user interface down to the state transitions of each hardware block. This insight is instrumental to drive hardware build readiness, system stability in the pre-silicon and NPI phase, and convey the overall system stability impact to engineering teams with potential solutions for optimization. Strong problem-solving skills and effective communication are critical for success in this role.
Responsibilities
In this role, you will constantly be challenged to learn about how Apples latest features and technologies work and collaborate with teams to enable this exceptional technology across the Software/Hardware/Silicon organizations. We work with teams to help them identify focus areas, run experiments, analyze data, and develop tools to help achieve efficiency while maintaining a great user experience.
Description:
Work cross-functionally with silicon, hardware, and software teams to help deliver surprise and delight in our latest products while enabling system development and stability. This role requires the technical depth and expertise to understand how things work from the user interface down to the state transitions of each hardware block.
This insight is instrumental to drive hardware build readiness, system stability in the pre-silicon and NPI phase, and convey the overall system stability impact to engineering teams with potential solutions for optimization.

The role includes development of Automated TEST Equipment (ATE) TEST stations, including digital tests and RF tests. The engineer will be responsible for TEST system development from the requirements definition stage through delivery of the TEST system to the customer and its maintenance. The role also includes technical characterization and definition of project documents such as SPEC, SOW, TRD. Education Required: Bachelors degree in Electrical Engineering.

You'll be joining the Israeli team which is the core center of our SW and ASIC design. You'll be part of the group driving our groundbreaking next-generation network devices. Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs. Join a team of dedicated engineers with a proven track-record at delivering breakthrough products. Our R&D center is outstanding - hosting all silicon HW and SW development teams inside one site. We are transforming the industry and building a new AI/ML Networks, as well as providing a unified, programmable silicon architecture that is the foundation of all our future routing products. Our devices are crafted to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed (50+ Terabits per second) without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

We are a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine! You have a unique opportunity to join the core center of our SW development and work with us to design and deliver breakthrough technologies

What You'll Do:

You'll be joining our Physical Design team, which is at the center of the silicon development. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.

We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

We are seeking a CAD Engineer to join the Physical Design team.

You'll be joining our Physical Design team within us, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

As part of the Architecture team, you will:
Directs, leads, and manages the technical activities of a hardware development function for electronic design, mechanical design and/or hardware reliability.
Directs, leads, and manages the technical activities of a software development function for software systems, applications and/or software quality assurance.
Directs, leads, and manages the technical activities of an integrated hardware/software systems design function.
Define device specifications and architectural features for next-generation networking silicon.
Design and implement logic and software solutions that meet performance, power, and scalability requirements.
Develop software components in C++ as part of the silicon architecture and enablement flow.
Collaborate closely with design, verification, and software teams to translate specifications into working silicon.
Contribute to the development of a unified and programmable silicon architecture enabling AI-driven networks.
Take part in shaping our products that power the Internet of the future.

As a key member of the team, you will be responsible for developing a state-of-the-art functional simulator for the family of devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.

In this role, you will:

Collaborate closely with the ASIC Architecture team to implement an accurate and efficient software model based on the architecture specifications.

Partner with both Software and Hardware design teams, providing support as they use the simulator as the golden reference for hardware implementation.

Ensure the simulator meets the highest standards of performance, reliability, and usability.

Contribute to defining best practices and methodologies for model development, validation, and integration. 

As a key member of the team, you will be responsible for developing a state-of-the-art functional simulator for the family of devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market for our solutions.

In this role, you will:

Work under the guidance of senior engineers to help implement and maintain components of the simulator based on architecture specifications.

Collaborate with the ASIC Architecture, Software, and Hardware teams to understand requirements and support their use of the simulator as a reference for development.

Participate in troubleshooting, testing, and validating simulator functionalities.

Learn and apply industry best practices in model development and integration. 

Your Impact:
Write and review micro-architecture specifications.
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements.
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure.
Work with the physical design team to close timing and PnR issues.
Support design methodology evolution and best practices.
Perform debug, root-cause analysis, and post-silicon validation in the lab.

Physical Design team within us is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Your Impact
You'll be part of the team, which is at the heart of our software and ASIC design efforts.

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

As a key member of the team, you will be responsible for developing a state-of-the-art functional simulator for the family of devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market for our solutions.


In this role, you will:

As a Senior engineer you will implement and maintain components of the simulator based on architecture specifications.

Collaborate with the ASIC Architecture, Software, and Hardware teams to understand requirements and support their use of the simulator as a reference for development.

Participate in troubleshooting, testing, and validating simulator functionalities.

Learn and apply industry best practices in model development and integration.