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we are hiring a CX Manager with deep expertise in ERP finance systems, P2P workflows, and integrations.
This role is the ERP SME and integration owner within Customer Experience. The focus is to understand how finance processes work in customer ERPs, how they connect , and how to turn customer issues, bugs, feature gaps, and new requirements into clear integration solutions.
This is a hands-on role for someone who can solve complex customer issues, define ERP integration requirements for Engineering, and lead resolution end to end. The role also operates in a highly AI-enabled environment, using AI tools, platforms and agents to improve triage, analysis, escalation management, and communication.
This role owns ERP integration within Customer Experience: diagnosing customer issues, defining integration requirements, and driving resolution end to end.
Youll partner with teams in Israel and the US and report to the Director of Customer Experience.
What You Will Do:
Own ERP integration issues across bugs, feature gaps, and customer requirements.
Serve as ERP SME and L3 support lead for complex finance workflow and integration cases.
Diagnose setup, configuration, data flow, mapping, permissions, and sync issues.
Distinguish between customer setup issues, integration issues, and product issues, and drive the right resolution path
Define functional requirements and solutions for ERP integration fixes, sync issues, missing data flows, and new capabilities.
Lead escalations with strong ownership and clear internal/external communication.
Use AI tools to improve triage, analysis, RCA, summaries, and handoffs, with clear human-review checkpoints.

As we expand our presence in Israel, we're seeking a visionary Junior Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Junior Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing.

Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness.

Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation.
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity.
Leverage scripting and automation to make engineering environment faster and more robust.

We are looking for entrepreneurs with deep finance, fintech and ERP experience who bring strong product judgment.
This role is for people who have lived finance systems complexity firsthand and want to use that experience to build product. You might come from finance transformation, ERP, consulting, operations, or fintech. What matters is that you understand where workflows fall short, where controls matter, how better systems should work, and how product decisions create business value.
AI-native tools are part of how we build. This role is a chance to turn finance and ERP insight into product faster, with more context and better judgment than traditional product development allows. Youll collaborate closely with teams across the Bay Area and Israel.
What You Will Do
Find high-value opportunities in fintech and ERP workflows that should be redesigned, not just improved
Shape those opportunities into clear product direction with strong user and business value
Define workflow logic, edge cases, controls, exceptions, and handoffs
Decide what should be automated and what should remain human-driven
Work with engineering, design, data and marketing to build and ship new capabilities
Test ideas with customers, learn quickly, and refine fast
Own the path from problem identification to customer value and business impact

As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling our products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities
Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing.
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration).
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices.
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints.
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance.
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets.
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp.
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews.

As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a DFT Engineer, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy
Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices

Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements

Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools