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We are seeking an experienced Atlassian Administrator (Jira, Confluence, JSM) to support our implementation of Atlassian Data Center and Cloud environments. Join our exceptional Business Information Systems Group, which manages Atlassian and other ALM tools to support all areas of the organization, from R&D to Operations!
What will your job look like:
Design, develop, and maintain software applications to meet organizational needs as a Jira/Atlassian Admin.
Administer Jira, Confluence, and JSM, including the creation and management of custom, complex projects, workflows, permission schemes, custom fields, dashboards, and reports.
Collaborate with various Jira and Confluence add-ons, such as Structure, ScriptRunner, Automation for Jira, CF++, JMWE, Xray, etc.
Develop a comprehensive understanding of the business processes supported by Jira.
Work closely with the Integrations team to design and implement integrations between the tools.
Gather requirements and improve business process workflows in Jira and Confluence, identifying functionality gaps.
Conduct training sessions for employees on how to effectively use Jira and Confluence, including new features.

You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our company EyeQ ASIC products. We are looking for a talented and motivated Masters graduate in Electrical Engineering, with strong interest in Electromagnets and Microwaves, to join our Power Integrity team at our company.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of our company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities we are a single SI/EV team is another strong advantage, enabling joint simulation-measurements efforts.

Join us for a meaningful and impactful role in safeguarding homeland security.

Role Description:

Develop and maintain complex ETL/ELT processes and Data Pipelines.
Work with Data Warehouses and Data Lake infrastructures.
Integrate diverse data sources while ensuring data quality, availability, and reliability.
Optimize and improve performance of processes and queries.
Collaborate closely with Analysts, Data Scientists, and development teams to deliver data-driven decision support solutions.

We are looking for a skilled and motivated C# Developer to join a professional development team working on complex and large-scale Enterprise systems.
This is an opportunity to work in a modern technological environment with challenging, performance-oriented development.

Responsibilities:

Join a development team responsible for a large-scale Enterprise system
Develop and maintain backend components of the system
Work with Microservices architecture, Multi-Threading, databases, and communication protocols
Develop using .NET Core (C#)
Work with MongoDB and occasionally contribute to the frontend using Angular

we are at the forefront of developing autonomous driving systems. our company state-of-the-art ECUs are integrated into vehicles from leading OEMs and enable its leading autonomous driving solutions. OPG group is responsible for Camera sensors roadmap and approvals, Camera Optics work and Image Quality Specification and Evaluation. OPG group is also responsible for Architecture of the optical path the subsystem that resides between the sensors and our companys SOC(SerDes, MIPI interfaces, etc.) The groups work scope includes Product requirements, System Architecture, Image Quality, Lens and optical design, Camera sensor selection and specification, Supplier management and close collaboration with Tier1 companies. As OPG Manager you will oversee these domains and manage several teams that work on these topics and be part of Platform Product and Architecture organization in our company. By joining us, youll collaborate with top engineers to develop innovative systems that not only shape the evolution of our industry-leading products, but also contribute to advancing the future of mobility. As part of our mission, youll play a key role in making the world a safer place through autonomous driving technology.
What will your job look like?
Lead a group that sets camera products definitions: Lead a group of a few teams, that defines and influences our companys camera products requirements, specifications and roadmap. The group deals with product and architecture definitions in professional fields such as Optics, Sensors, Image quality and related interfaces (e.g. MIPI, SerDes).
Be responsible for: Camera sensors specification and roadmap, Optical design and specifications, Image quality metrics, KPIs and evaluations.
Engage with vendors :Analyze and understand OEM requirements and maximize alignment with existing solutions.
Collaborate with SW and HW development teams.
Collaborate with BizDev: For new projects, work together with business development to assure new designs comply with company road map. Introduce new sensors to our company roadmap addressing new market needs.
Work closely with Project Managers: Define, map dependencies, and prioritize the scope of work.
Innovate with Sensing, Driving and Fusion teams: To optimize overall system performance.

we are at the forefront of developing autonomous driving systems. our company state-of-the-art ECUs are integrated into vehicles from leading OEMs and enable its leading autonomous driving solutions. OPG group is responsible for Camera sensors roadmap and approvals, Camera Optics work and Image Quality Specification and Evaluation. OPG group is also responsible for Architecture of the optical path the subsystem that resides between the sensors and our companys SOC(SerDes, MIPI interfaces, etc.) The groups work scope includes Product requirements, System Architecture, Image Quality, Lens and optical design, Camera sensor selection and specification, Supplier management and close collaboration with Tier1 companies. As OPG Manager you will oversee these domains and manage several teams that work on these topics and be part of Platform Product and Architecture organization in our company. By joining us, youll collaborate with top engineers to develop innovative systems that not only shape the evolution of our industry-leading products, but also contribute to advancing the future of mobility. As part of our mission, youll play a key role in making the world a safer place through autonomous driving technology.
What will your job look like?
Lead a group that sets camera products definitions: Lead a group of a few teams, that defines and influences our companys camera products requirements, specifications and roadmap. The group deals with product and architecture definitions in professional fields such as Optics, Sensors, Image quality and related interfaces (e.g. MIPI, SerDes).
Be responsible for: Camera sensors specification and roadmap, Optical design and specifications, Image quality metrics, KPIs and evaluations.
Engage with vendors :Analyze and understand OEM requirements and maximize alignment with existing solutions.
Collaborate with SW and HW development teams.
Collaborate with BizDev: For new projects, work together with business development to assure new designs comply with company road map. Introduce new sensors to our company roadmap addressing new market needs.
Work closely with Project Managers: Define, map dependencies, and prioritize the scope of work.
Innovate with Sensing, Driving and Fusion teams: To optimize overall system performance.

we are looking for an experienced C# Frontend Developer to join a team developing advanced simulation systems with significant impact on national security.

Whats the role?

Frontend development in C# using WPF, WinForms, and XAML
Working on complex operational systems in a Near Real-Time environment
Developing very rich and advanced user interfaces (UI)
Maintaining and extending large-scale legacy systems
Collaborating within a diverse development team in a dynamic work environment with cross-functional interfaces
Working with Oracle DB

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Participate in the development of flows & methodologies from Synthesis , Place& Route & all signoff flows.
Plan & execute flow releases, coordinate & track development tasks.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new tools features and methodologies to bring innovation with significant RoI.
Hands-on physical design block ownership end to end, from Synthesis floor planning, Place & Route with target to achieve best PPA.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Serve as the technical lead while mentoring and guiding team members.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Lead the development of flows & methodologies from Synthesis, Place & Route & All signoff flows.
Plan & execute flow releases, coordinate & track development tasks between the team.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Serve as the technical lead while mentoring and guiding team members.

Which department will you join? our company's VLSI team - a group designing the EyeQ chips for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering. Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Engineer to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block or IP owner from RTL to GDS with horizontal domain ownership.
Collaboration with front-end and architecture teams to address issues, define design methodologies and improve QoR & convergence.
End to End ownership from Synthesis, DFT insertion, Floor Planning , Place & Route till signoff.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Exploratio of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Technical support and mentoring the engineers in the team.

our company's EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Layout activities for complex Sub Full Chip with several levels of hierarchies.
Floorplanning, top-down deliveries & bottom up rollup , Sub FC/ IP level integration & verification.
Signoff on all physical design domains PV, IR/EM, LEC, LP Verification.
Physical Verification expert, building, maintaining and enhancing the flow for new technologies, improving reliability & convergence ToT.
Servings as a technical expert while mentoring and guiding team members,
Hands-on physical design block owner from RTL to GDS , an option.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.

You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our company EyeQ ASIC products.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop Layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of our company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities - we are a single SI/EV team - is another strong advantage, enabling joint simulation-measurements efforts.