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Our Algorithm Research & Development team operates at the cutting edge of Cyber over RF (CRF) - a unique and multidisciplinary field that blends signal processing, RF experimentation, physics-based modelling, and cyber research.
We work end-to-end: from early-stage research and concept development, through algorithm design and simulation, all the way to lab prototypes and real-world field testing. Its hands-on, intellectually demanding, and incredibly rewarding.
Were looking for a passionate engineer with a strong foundation in signal processing and an appetite for solving complex, real-world problems.

you will define system and IP architectures, develop architectural models, and author technical specifications for a variety of high-performance, high-quality, low-power, world-class products.

You will

Define and drive architectures across multiple domains, spanning chip-level components, subsystems, and system-level workflows.

Translate product requirements into architectural specifications, features, and hardware/software execution models for implementation teams.

Lead cross-functional technical decisions, balancing functionality, performance, scalability, power, and implementation trade-offs.

Experienced DSP & AI Development Engineer

Engineering, DSP, Communications, AI, Embedded Software, Algorithms

Location Israel - Hod HaSharon

Responsibilities
Design and develop high‑performance DSP software, including highly efficient kernels for different applications, such as communication algorithms and machine learning inference workloads

Implement optimized, low‑level DSP solutions with a strong focus on performance, accuracy, and real‑time constraints

Deliver high‑quality, efficient, and well‑tested code according to project schedules

Collaborate closely with team members and peer teams across multiple engineering disciplines

Next-gen Communications DSP & AI Software Development Engineer

Job Area

Engineering, DSP, Communications, 5G/6G, Algorithms, AI, Embedded Software

Location

Israel - Hod HaSharon

Responsibilities
Design and develop high-performance DSP software and optimized vector-processing kernels for wireless communications and AI workloads.
Implement low‑level DSP software with strong focus on performance, accuracy, and real‑time constraints.
Deliver high-quality, maintainable, and well-tested code while meeting project milestones.
Collaborate with team members and peer teams across multiple engineering disciplines.

We are seeking a seasoned Sr Staff Physical Design Engineer to provide technical leadership across full-chip and multi-die physical implementation on advanced TSMC FinFET nodes. You will define and own the backend design methodology, champion Agentic AI integration into the PD flow, and mentor engineers across the team while interfacing directly with foundry, EDA vendors, and executive stakeholders.

What You'll Do
Architect and own the full-chip physical design strategy: floorplanning, power delivery network (PDN), clock architecture, PnR, and timing closure
Define and drive backend methodology standards across the team for advanced node tapeouts (N5/N4P/N3)
Lead critical timing closure efforts - MCMM, OCV, advanced ECO strategies, and cross-corner sign-off
Oversee and guide signal integrity, power integrity, EM/IR, and reliability analysis for full-chip designs
Architect and lead the development of scalable PD flow infrastructure using Python and TCL - including automated regression, sign-off reporting, and run management systems
Champion the adoption of Agentic AI in the design flow - define use cases, evaluate tools, prototype autonomous agents for floorplan exploration, timing closure, and ECO automation
Lead cross-functional design reviews with DFT, verification, analog, and process engineering teams
Interface with TSMC, EDA vendors (Synopsys, Cadence, Siemens), and internal research teams to evaluate and adopt new methodologies
Mentor and technically guide junior and mid-level PD engineers across the organization

We are seeking a motivated FPGA Engineer with up to 3 years of experience to join our hardware development team. In this role, you will contribute to the design, implementation, verification, and debugging of FPGA-based solutions for advanced digital systems. You will collaborate with architects, ASIC/SoC designers, firmware engineers, and verification teams to develop high-performance products from concept through deployment.

This position offers an excellent opportunity to gain hands-on experience with modern FPGA technologies, digital design methodologies, and complex microcontrollers in a collaborative engineering environment.

Key Responsibilities
Design and implement FPGA logic using Verilog and SystemVerilog.

Develop and maintain FPGA subsystems, IP blocks, and reference designs.

Participate in FPGA architecture discussions and design reviews.

Perform RTL simulation, debugging, and functional verification.

Support synthesis, place-and-route, timing closure, and implementation activities.

Develop and execute test plans for FPGA validation and bring-up.

Debug hardware and system-level issues in laboratory environments.

Integrate interfaces such as JTAG, AHB, DDR, etc.

Collaborate with software, firmware, and hardware teams throughout product development.

Document designs, verification results, and development procedures.

Support prototype development and system integration activities.

As a Senior RTL Verification Engineer, you will lead the verification of complex subsystems and architectural features within a next-generation, high-performance RISC‑V Application Processor. You will work closely with architecture, design, modeling, software, validation, and implementation teams to ensure first-pass silicon success while meeting aggressive performance, power, and area (PPA) targets.

In this role, you will drive verification strategy, methodology, and execution from specification through tape-out, providing technical leadership in the definition of scalable verification environments, coverage closure plans, and debug methodologies. You will be expected to independently own large verification domains, influence design and architecture decisions, and mentor junior engineers.

The ideal candidate has extensive experience in CPU or SoC verification, with strong expertise in one or more of the following areas: RISC‑V architecture, CPU microarchitecture, MMU, memory hierarchy, cache coherence, interconnects, and micro-controller verification.

Responsibilities

Lead verification efforts for complex CPU and SoC subsystems from architecture definition through tape-out.

Define comprehensive verification strategies, test plans, coverage models, and closure criteria.

Architect, develop, and maintain advanced UVM-based verification environments and reusable verification components.

Drive verification execution, including stimulus development, functional coverage closure, assertions, regressions, and debug.

Collaborate closely with architecture and design teams to review specifications, identify ambiguities, and ensure verifiability.

Develop constrained-random, directed, and scenario-based tests to validate functional correctness and corner cases.

Drive root-cause analysis and resolution of complex design and verification issues.

Define and implement verification methodologies that improve scalability, quality, and productivity across the project.

Work with software, modeling, performance, and validation teams to develop system-level verification solutions.

Analyze verification metrics and risks, proactively driving closure plans to achieve project milestones.

Mentor junior verification engineers and contribute to the technical growth of the team.

Contribute to DV methodology discussions and influence verification best practices across the organization.

our company is a leading supplier of custom SOC and security hardware solutions for the computing and server markets. We are looking for a highly experienced CAD Engineer from the semiconductor industry to join Nuvoton as a key contributor. In this role, you will help modernize and upgrade our design environment, EDA infrastructure, and in-house CAD tools to support advanced technology nodes, improve engineering efficiency, and enable future growth. You will also play a key role in supporting the design and verification activities of current and future semiconductor projects.

Join us in building next-generation embedded systems for the automotive industry.
We are looking for a hands-on Embedded Team Lead with strong technical expertise and leadership experience to drive the development of complex real-time systems.
Your D2D will include:
Lead and mentor an embedded development team
Define software architecture for complex embedded systems
Drive high-quality development processes and best practices
Own delivery, planning, and execution of team objectives, as agile scram master
Stay hands-on (~70%) in development (C/C++)
Ensure performance, reliability, and code quality
Work closely with cross-functional teams on cutting-edge automotive solutions

Join our kernel team, in charge of the network segmentation: building real-time kernel-level enforcement and telemetry for next-generation security products, as well as a new AI Detection and Response (AI-DR) initiative. Youll develop production-scale software across Linux, Windows, and other platforms, solving complex security challenges. As part of the small senior leaders of the team, youll have a direct impact on the product and its technical direction.
As a Principal Kernel Engineer , you will be responsible for:
Writing and debugging kernel-level C code across our Linux kernel module, Windows kernel driver, and eBPF programs.
Owning end-to-end debugging of complex production issues, including kernel crashes and low-level system failures, while driving root-cause analysis and post-mortems for production environments.
Acting as the technical lead for a small team by reviewing critical kernel/eBPF code mentoring engineers, unblocking complex issues, and guiding key technical decisions.

we are looking for a Senior Full-Stack Software Engineer.
As a Senior Software Engineer, you will be responsible for:
Designing and building scalable backend applications for next-generation identity solutions.
Collaborating with Product Management and engineering teams to deliver high-quality features.
Conducting design reviews and partnering with QA to deploy production code.
Collaborating across the organization with Data Science, Product, and Operations to build innovative components of Akamai's Big Data AI solutions.
Solving complex technical challenges proactively with a high success rate.
Participating actively in agile SCRUM planning and technical team meetings.
Optimizing and supporting the continuous integration and delivery pipelines.

At Infinidat, a Lenovo company, we empower enterprises and service providers with cutting-edge storage platforms that redefine performance, reliability, and cyber resilience at scale. As a Senior System Test Engineer, you will take part in ensuring the quality of INFINIDAT's revolutionary, enterprise-grade storage system, including its software suite, and infrastructure. You will participate in the whole life-cycle of products and versions, working closely with the company departments – from Product Requirements, through R&D and Test Automation development, to Professional Services and Support.

Responsibilities:

* Participate in E2E R&D processes, requirements, development, and test design reviews.
* Setup and maintain complex testbeds for System, HW, Scale, and High Availability testing.
* Creatively construct and rigorously investigate challenging test scenarios.
* Exercise our enterprise-grade storage servers to their limits by: -Designing, scripting, and running high-end load-generators and other state-of-the-art test equipment -Running test suites from our extensive library of automated tests.
* Python-based automated tests and test equipment to exercise our enterprise-grade storage to its limits.