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We are a strong, fast-moving group developing advanced solutions in some of Palo Alto Networks most innovative areas - the Cortex Platform. Were looking for an exceptional Senior Frontend Engineer with deep technical skills and a passion for creating exceptional user experiences. Youll join a team that values clean, scalable architecture and high-quality code, working closely with product, UX, and backend teams to deliver impactful features that protect our customers from evolving cyber threats.
Key Responsibilities
Design and develop next-generation, scalable frontend applications on the Cortex platform.
Lead the development of key frontend components, taking ownership from conception through to deployment in a dynamic, agile environment.
Proactively collaborate with UI/UX experts, product managers, and backend engineers to translate complex requirements into visionary cybersecurity products.
Research, design, and implement sophisticated and complex data visualization solutions to make security data understandable and actionable.
Uphold high standards for code quality and architecture through rigorous code reviews, automated testing, and advocating for frontend best practices.
Mentor junior engineers and contribute to a culture of continuous learning and technical excellence within the team.
Analyze and optimize application performance to ensure a responsive and seamless user experience for our customers.

Required Senior DFT Lead
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next-generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Collaborate with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Oversee DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

As a Technical Program Manager (TPM) in the R&D PMO team. You will bridge the gap between large-scale organizational architecture and processes and modern, automated execution. You will be responsible for designing, implementing, and scaling critical cross-functional processes-such as R&D planning, dependency tracking, and operational governance-across multiple engineering and product divisions. You are proactive leader and an AI-fluent builder. You will lead complex stakeholder alignment across different groups, but you will also actively leverage AI workflows, low-code automations, and modern tooling integrations to bake your processes directly into our R&D environment. Your goal is to deliver operational solutions while permanently eliminating manual "administrative tax" for our developers.
Your Impact
Architect Cross-R&D Operating Models: Lead the end-to-end design, rollout, and optimization of massive cross-functional frameworks (e.g., quarterly/annual planning cadences, execution governance, and cross-team dependency mapping) aligning cross R&D teams with core business priorities.
Drive Stakeholder Alignment & Change Management: Serve as the central pivot across Engineering and Product functions. Navigate conflicting priorities, build high-trust alignment, and coach diverse teams through organizational changes.
Programmatic Process Automation: Actively explore, prototype, and implement smart tooling, API integrations, and AI-driven workflows to automate data aggregation, status tracking, and reporting-ensuring operational consistency without sacrificing developer velocity.
Optimize R&D Effectiveness: Mine and analyze R&D delivery metrics, telemetry, and performance data to identify systemic friction points. Deploy scalable engineering-adjacent solutions rather than adding manual check-ins or status meetings.

Required Silicon Validation Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We are building a new team to lead the post-silicon validation efforts for our product. We are looking for highly motivated and talented engineers to join us in ensuring the quality and functionality of our next-generation networking silicon. This is a unique opportunity to be part of a foundational team and make a significant impact.
As a Silicon Validation Engineer at Cloud, you will play a pivotal role in the validation of our custom silicon solutions that power our cloud infrastructure bringing it to the highest quality level. Your expertise in post-silicon validation will be essential in identifying and resolving issues before they impact our customers, ensuring a seamless and high-performance cloud experience.
Responsibilities
Dive into the architecture and microarchitecture of complex hardware units and features, such as packet processing pipelines and advanced networking capabilities.
Develop comprehensive post-silicon validation test plans based on a thorough understanding of the design and specifications.
Write, execute, and debug validation tests using Python or C/C++, running on Pre-Si emulation platforms and primarily on the silicon.
Lead the bring-up, troubleshooting, and debug efforts on silicon, identifying root causes of hardware and software issues.
Collaborate closely with Architects, Designers, and other teams to drive bug fixes and ensure feature functionality.

abra is seeking for an MLOps Engineer . This role requires Senior ML Platform Engineer (MLOps) to maintain and improve the infrastructure that turns AI into reliable, secure, production-grade capabilities in an air-gapped environment. You'll maintain and develop the platform layer for modern AI\ML systems: training and fine-tuning pipelines, model serving, evaluation infrastructure, experiment tracking, model registries, vector databases as part of RAG workflows, dataset versioning, and GPU orchestration with a strong focus on open-weight LLMs and mission-critical inference where data, models, and infrastructure remain fully controlled by the organization. This is a hands-on role for someone who understands both ML/AI workflows and production infrastructure, and who can partner with AI developers, data scientists, security teams, and product engineers to upkeep a low-friction yet highly secure AI platform.

As a Software engineer on our Email Security team, you will play a key role in shaping and delivering a cutting-edge email security solution within the Cortex platform. Your responsibilities will include designing and developing an infrastructure capable of supporting billions of events per second, collecting, storing, processing, analyzing, detecting threats and making them accessible, visible and actionable for users while seamlessly integrating with the industrys leading cyber-security products. You will design and build a highly available, reliable, and secure solution that adheres to the highest standards. Beyond development, your crucial role involves meaningful cross-organizational collaboration, driving a significant impact to ensure the success of our product. Our Cortex engineering group, primarily based in the TLV office, allows us to operate at a high pace with short decision-making loops. In this role, you will need to demonstrate creativity, innovation and deep knowledge in backend engineering, conducting research to find new technologies. A can-do approach, a passion for excellence and a commitment to continuous improvement are essential qualities for success in this position.
Key Responsibilities
Take ownership of a brand new product, driving its development from concept and design to full implementation
Focus on meaningful, high impact work, building major parts of a groundbreaking new product
Build a new offering designed to operate at massive scale
Dive into new cutting-edge technologies, researching and integrating them to enhance the products capabilities.

Required SoC Test Automation and Infrastructure Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Test (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips.
You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices, drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs
Responsibilities
Provide tools, set the environment and create automation to silicon engineering (SiEng) teams, collaborate with Test, Product, quality and reliability (Q&R) and system-level test (SLT) teams.
Create smooth and effective ways to manage silicon engineering (SiEng) datastream to and from suppliers and internally, between different platforms, while optimizing formats and datalogs, convert per need.
Verify test solutions on pre-silicon models (simulation or emulation) and support Automated Test Equipment (ATE) test development setup and environment.
Develop test method for ATE platforms.
Provide pre and post silicon dashboards and indicators that will reflect the status, demonstrate progress and point on the gaps.