לוח משרות דרושים מדעים מדוייקים, לחיפוש זה נמצאו 529 משרות

we are looking for best-in-class chip Verification engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you'll be doing:
own end-to-end unit-level (ul) verification of complex chip blocks, from verification planning through coverage closure
work closely with architecture and micro-architecture teams to review specifications, identify gaps and corner cases, and ensure the design is fully verifiable
develop verification strategies, environments, checkers, assertions, and coverage to validate functional and micro-architectural requirements
drive verification of complex scenarios, including feature interactions, error flows, performance-related behavior, and corner cases.

we are hiring a senior physical Verification engineer to lead signoff-quality verification for advanced silicon programs. you will drive physical verification strategy and closure for complex designs, working across implementation, methodology, and signoff teams to achieve tapeout readiness. the role requires strong technical ownership, structured debug, and the ability to scale best practices across multiple programs. this is a great match for an engineer who wants to combine technical depth with broad project impact.
what you'll be doing:
own physical verification closure for major blocks or full-chip designs through tapeout.
lead debugging of complex drc, lvs, and reliability-related issues and drive high-quality resolution.
define verification check plans, signoff criteria, and closure priorities with cross-functional teams.
partner with physical design, custom design, and cad teams to improve quality and turnaround.
drive automation, methodology improvements, and best practices for scalable pv execution.
review results, coach team members, and help reduce repeated classes of violations.
we are committed to fostering a diverse work environment and proud to be an equal opportunity employer. as we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. we will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. please contact us to request accommodation.

job overview:
as a senior Verification engineer, you will join the gpu hardware verification team in raanana, israel, responsible for verifying mali graphics processors - the worlds most widely shipped gpu. in this role, you will contribute to the development of next-generation gpu technology by implementing advanced verification methodologies, building robust verification environments, and collaborating closely with architecture, design, and product teams to deliver high-quality ip.
responsibilities:
define and develop verification plans and strategies for complex gpu components and subsystems.
design, implement, and maintain verification environments using systemverilog and uvm.
develop verification infrastructure including agents, testbenches, and reusable components.
analyze coverage, debug complex issues, and drive closure of verification goals.
collaborate with architecture, design, and product teams to ensure functional correctness and product quality.
required skills and experience:
b.sc. in electrical engineering, computer engineering, Computer Science, or a related field.
5+ years of experience in hardware verification, including methodology development and implementation.
strong knowledge of systemverilog and uvm-based verification environments.
experience with random and coverage-driven verification techniques.
experience working in Unix / Linux environments, including scripting (e.g., Python or PERL ) and ci workflows.
nice to have skills and experience:
experience with our processors or gpu architectures.
knowledge of design for verification (dfv) techniques.
background or exposure to logic design.
our 10x mindset
we believe progress happens when people are empowered to think bigger and push beyond what seems possible. our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. we learn fast, prioritise collaboration and turn bold ideas into real technology. we look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed.
use of ai in your application
we embrace the benefits ai can bring, including in recruitment. you may use ai to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. however, your application and interview responses must reflect your own thinking, experience, and abilities. we want to understand your authentic perspective, creativity, and approach to problem solving. as such, you may not use ai to complete assigned tasks as part of any assessments.
recruitment adjustments and accommodations
we want to build extraordinary teams. to note, by sending us the requested information, you consent to its use by us to arrange for appropriate accommodations. all accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. please email us about anything we can do to accommodate you during the recruitment process.
hybrid working
our approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. we believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs. details of what this means for each role will be shared upon application. in some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution.

we are looking for an excellent, highly motivated sw verification manager to join the software verification team in the data processing unit (dpu) sw group. in this role, you will lead a team of highly skilled Verification engineers, combining people management, technical leadership, and execution. we are looking for a candidate with a strong quality-oriented mindset, the ability to thrive in an environment with complex software and hardware designs, and a passion for deep-dive verification of key dpu components. the role includes working closely with hw, fw, and sw teams all over the world, and taking our product to next level.
what you'll be doing:
lead, mentor, and grow a team of software Verification engineers, fostering a culture of technical excellence, ownership, and professional development.
provide technical leadership and hands-on mentorship, driving the design and implementation of comprehensive verification plans and automated environments using Python.
lead end-to-end feature validation, from architectural review to final system integration, ensuring robust hw-sw interoperability for high-end hardware and software.
ensure high product quality by conducting code reviews, defining engineering procedures, and identifying, analyzing, and reporting software defects.
drive improvements for performance, quality, and stability around sw acceleration solutions, taking an active part in integration and verification with r&d.
partner closely with cross-functional teams (hw, fw, sw architectures, and product) across multiple engineering organizations worldwide.

in this role, you will build and lead a team of validation engineers, owning the strategy, methodology, and execution of simulation-based validation frameworks that ensure our networking solutions meet the highest standards of quality, scale, and real-world applicability before reaching customers.
what you'll be doing:
leading and managing a team of network validation engineers responsible for end-to-end validation of our customer-facing networking solutions at scale, using a dedicated e2e simulation cluster environment.
defining the overall validation strategy and roadmap - establishing simulation methodologies, TEST coverage frameworks, and quality gates that align with product milestones and customer use cases.
pioneering the use of agentic ai flows within the validation organization - leading the team to design, build, and operate ai-driven agents capable of autonomously performing regression analysis, identifying coverage gaps, generating new TEST cases, and implementing validation code. these agentic workflows will continuously learn from simulation results and product changes, dramatically accelerating the team's ability to scale TEST coverage and respond to emerging quality signals without manual intervention.
overseeing the design and continuous improvement of automated regression suites for networking protocols and large-scale simulation runs, ensuring scalable, repeatable, and high-confidence validation outcomes.
establishing a rigorous regression analysis culture - guiding the team in identifying trends, root causes, and systemic coverage gaps, and ensuring timely resolution in collaboration with engineering stakeholders.
serving as the primary validation partner to design, architecture, and ncs teams - translating solution requirements into simulation scenarios, providing early-cycle quality feedback, and influencing product direction.
analyzing customer-reported networking solution issues, driving TEST gap analysis, and ensuring robust regression coverage that prevents recurrence.
staying current with emerging networking standards, simulation technologies, and industry best practices to continuously evolve the team's validation capabilities.

are you ready to make a significant impact by tackling sw verification challenges? our networking is seeking an exceptional candidate to work with world-class technologies in the domains of high-speed communication and virtualization for our most advanced markets and customers. our products encompass ethernet and infiniband protocols, delivering a wide range of cutting-edge networking, Storage, and security services for cloud, complex compute, and ai workloads. as a software Verification engineer, you will play a crucial role in ensuring on-time and high-quality releases.
what you'll be doing:
take an active part in development, integration, and verification with r&d
develop and maintain TEST automation frameworks and scripts using Python
identify, analyze, and report software defects, inconsistencies, and other quality issues
drive design verification flows and methodologies improvements
perform functional, integration, and regression of software applications and networking protocols
work with planning and tracking systems to manage the release progress and build release indicators
participate in code reviews, provide feedback, and suggest improvements to enhance the quality and maintainability of the software
continuously monitor and evaluate the effectiveness of TEST processes and methodologies, recommending improvements as necessary
stay up to date with industry best practices, new technologies, and emerging trends in software verification and QA
make better product quality by improving TEST coverage

our chip design group is looking for best-in-class Verification engineers to join our outstanding silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovative chips, and enjoy working in a meaningful, growing, and highly professional environment where you make a huge impact in a technology-focused company.
what you'll be doing:
verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to performance.
daily work involves acquaintance with all aspects of chip development: design, micro- architecture, firmware, production, and verification.
engage in cutting-edge pcie generation working on latest pcie gen7.

our team in israel is looking for a senior hardware Validation engineer to join the board design hardware team. the team leads the development of networking infrastructure for our next-generation data centers, focusing on accelerated performance and optimized end-to-end gpu connectivity. we are looking for a hands-on and detail-oriented practical engineer with strong lab skills, who enjoys working in a dynamic, multidisciplinary environment.
what you'll be doing:
perform board bring-up, validation, and debugging activities in the lab
operate lab equipment such as oscilloscopes, power supplies, logic/spectrum analyzers, and multimeters
support hardware investigations by reading schematics, analyzing layouts, and completing TEST procedures
document TEST results and communicate findings clearly to engineering teams
work closely with electrical, mechanical, thermal, and system engineers throughout the development cycle.

we are looking for an excellent senior firmware Verification engineer for our fw phy verification group. the person will be part of fw phy verification of our products. will closely work with our fw phy development, architecture teams and gain deep understanding of our products and technologies.
what you'll be doing:
own the responsibility for delivering networking features and their verification aspects.
define, develop and maintain verification infrastructure and regression tests suites - make TEST suites robust, maintainable and easy portable.
work with continuous integration system, regression tools, automate builds, run TEST suites and analyzing results.
innovate! bring our product to next quality level

we have been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. it's a unique legacy of innovation that's fueled by great technology-and amazing people. we are now seeking a highly motivated software verification manager to join our switching group, working on sonic network os. in this role, you will manage sonic verification team that will develop automatic tests and lead regression analysis for sonic os running over switches.
what you'll be doing:
lead and mentor sonic software verification team; set technical direction, define priorities, and grow team capabilities
design and implement robust, maintainable, and efficient automated TEST suite for sonic os which is an open-source nos
lead regression analysis for sonic nos following regression automated tests
cross-functional work with sonic design teams, QA, architecture, fw/sdk/sai/platform teams.

we are seeking a physical Verification engineer to help ensure our asic and SOC designs are clean, correct, and ready for tapeout. this role focuses on physical verification quality across layout data, connectivity, and manufacturing rule compliance. you will work closely with physical design, custom layout, and methodology teams to run verification flows, debug issues, and improve signoff robustness. this is an excellent opportunity for an engineer who enjoys detailed analysis and high-impact signoff work.
what you'll be doing:
run and analyze physical verification checks such as drc, lvs, and other tapeout-quality signoff checks.
debug physical verification violations and partner with design teams to drive clean closure.
review layout, netlist, and runset interactions to identify root causes and recommend fixes.
support full-chip and block-level verification readiness across implementation milestones.
improve physical verification flow quality, turnaround time, and automation.
collaborate with methodology, cad, and foundry-facing teams on rule interpretation and signoff quality.