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we are looking for a talented Hardware Engineer to join our development team. If you enjoy designing complex electronic boards, solving real-world system challenges, and working on cutting-edge defense technologies, we would love to hear from you.
Responsibilities:
Design and develop electronic boards and system hardware architecture.
Lead the full product lifecycle: concept, schematic, layout guidance, bring-up, and production.
Collaborate with cross-functional teams (software, mechanical, system, and integration).
Work with subcontractors and support performance analysis.
Participate in design reviews, system validation, and field testing.
Support the transition from development to manufacturing.

We are looking for a senior systems engineer with proven experience leading the design and development of an interceptor missile.
The systems engineer will take full responsibility for the interceptor missile from initial stages through deployment. A hands-on role in a young, growing company where deep engineering meets initiative, creativity, and a drive for performance.
Responsibilities:
Definition and design of the system architecture for an interceptor missile: sub-systems including the seeker, rocket engine, navigation and control systems, interface design, performance envelope definition, trials, and reliability tests.
Setting system requirements, writing engineering specifications (ICD, SRR, etc.), and working with the various development teams.
Leading system integration, conducting lab and field trials, and writing performance reports.
System-level risk management and supporting integration and production processes.
Interfacing with internal and external customers, suppliers, and quality and safety stakeholders.
Tracking and supporting the system throughout its lifecycle, including maintenance, updates, and support during operational deployment.

Were seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment - those who want to be part of the next generation of airspace security innovation.
Key Responsibilities:
Deployment & Integration
Lead end-to-end installation, configuration, and commissioning of EnforceAir Plus systems across diverse global operational environments, including military grade installations, border crossings, airports, and critical national assets.
Integrate EnforceAir Plus with third-party detection layers including EO camera arrays, radar sensors, Jammer and RF detection systems into unified C2 architectures
Validate detection zones, cyber-takeover workflows, and sensors fusion configurations against client operational requirements
Troubleshoot and resolve integration issues across hardware, software, RF, and network layers, both on-site and remotely
Customer Engagement & Technical Advisory
Act as the trusted technical advisor to customers stakeholders, throughout the full project lifecycle
Conduct site surveys, RF environment assessments, and infrastructure readiness reviews ahead of every deployment
Translate complex operational use cases and threat scenarios into system configurations and deployment architectures
Lead customer acceptance testing (SAT), sign-off procedures, and operational readiness reviews

We are seeking an experienced, highly technical Senior Hardware Product Manager to own the end-to-end product lifecycle, operational sustaining, regulatory qualification, and sales enablement for our deployment kits and complex hardware configurations. In this role, you will serve as the single point of truth for major strategic kit initiatives.
You will bridge hardware engineering, manufacturing scaling, regulatory compliance, and commercial execution- working cross-functionally across R&D, System Engineering, Operations, Quality, and Sales to drive physical product maturity, reliability, and market deployment.
Key Responsibilities:
HW Product Ownership & PLCM: Own the end-to-end PLCM policy for deployment kits, managing product roadmap, definitions and execution through release and ongoing lifecycle evolution.
Inbound Leadership: Drive internal initiatives and prioritize System, SW and HW team efforts to ensure aligned execution.
Domain SME: Serve as the primary technical subject matter expert for deployment form factors, environmental constraints, and hardware kit capabilities.
Operations & Sustaining: Sustain day-to-day hardware health including design for manufacturability, supply chain issue mitigation, production scaling support, and root-cause resolution of field hardware defects (RMAs) with Quality and R&D.
Compliance, Qualification & Certification: Oversee kit-level regulatory, military, and environmental testing such as FCC/CE, MIL-STD 810/461, EMC/EMF etc.
Sales Enablement: Drive domain-specific sales enablement, including marketing materials, user documents (Installation Manuals, ICDs, Product Descriptions), and technical support for presale and customer inquiries.

We are seeking a Communication PHY Algorithms Engineer.
This role is focused on the end-to-end research, design, and implementation of digital receivers for proprietary drone communication signals.
Responsibilities:
Mathematically characterize complex communication and signal detection problems. Analyze and assess design trade-offs based on both performance metrics and implementation complexity.
Develop and maintain simulations using MATLAB and Python.
Design digital receiver modules to be implemented either by FPGA of SW.
Implement features directly in SW or technically lead and verify the FPGA implementation efforts of the FPGA engineer.

We are seeking a highly skilled Senior Communication PHY Algorithms Engineer.
This senior role is focused on the end-to-end research, design, and implementation of digital receivers for proprietary drone communication signals.
Responsibilities:
Mathematically characterize complex communication and signal detection problems. Analyze and assess design trade-offs based on both performance metrics and implementation complexity.
Develop and maintain simulations using MATLAB and Python.
Design digital receiver modules to be implemented either by FPGA of SW.
Implement features directly in SW or technically lead and verify the FPGA implementation efforts of the FPGA engineer.
Accompany the integration process of the feature until its end-to-end operation.

Were seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment - those who want to be part of the next generation of airspace security innovation.
This role is focused on designing, developing, and maintaining advanced automation solutions across unit, integration, system, and end-to-end testing levels.
The ideal candidate is a hands-on developer with strong expertise in Python and Pytest, experienced in building and executing automated tests, and comfortable working with modern CI/CD pipelines and automation tools.
The Senior Developer will act as a technical mentor and key contributor, ensuring best practices are followed and test automation is seamlessly embedded into the development lifecycle.
Key Responsibilities:
Develop and maintain automated RF test development tools using Python and other relevant programming languages.
Configure, calibrate, and operate RF test equipment such as Vector Signal Generators (VSGs), Spectrum Analyzers (SAs), and related instruments.
Create and validate RF test setups for performance validation, debug, and system characterization.
Analyze test results, generate comprehensive reports, and present findings to cross-functional teams.
Collaborate with hardware and software engineers to integrate automated RF testing into the product development cycle.
Stay current with emerging RF technologies and testing methodologies, proposing and implementing improvements to existing test processes.
Contribute to the development of RF testing strategies aligned with R&D goals and product roadmaps.
Research and introduce innovative RF automation tools, frameworks, and workflows aligned with R&D goals.

Were seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment - those who want to be part of the next generation of airspace security innovation.
Key Responsibilities:
Lead complex, multi-system features and platforms from initial concept through design, implementation, and release.
Analyse, define, and debug complex system behaviours, state machines, algorithms, and event-response logic (including radio link budget considerations).
Define requirements and guide multi-disciplinary teams-spanning both our internal engineering groups (SW, HW, Modem, DSP, FPGA) and external vendors-through implementation, debugging, and integration.
Lead the integration of internal subsystems and optimize the integration of external vendor technologies.
Perform independent, hands-on debugging using Python or Matlab and log analysis tools.
Actively participate in, guide, and lead lab and field testing, validation, and system optimization both in the lab and in outdoor environments.

This is a great opportunity for a strong technical engineer to join a highly skilled Application Engineering team in a leading EDA company, working with cutting‑edge tools, advanced technologies, and the most innovative semiconductor companies in the industry.
The Application Engineer combines deep technical expertise with strong interpersonal and problem‑solving skills to support customers, drive technology adoption, and contribute to the successful deployment of Custom IC solutions.
The role involves close collaboration with customers as well as with R&D and Product teams to help define, improve, and proliferate new solutions.
Key Responsibilities:
Support customers adoption and effective use of Custom IC solutions.
Leveraging the Virtuoso environment and associated tools, to help customers address complex design challenges from concept to successful deployment.
Drive technical campaigns, product evaluations, and benchmarks within a customer‑facing and technically challenging environment.
Provide methodology guidance, best‑practice recommendations, and technical problem resolution
Work closely with customers to understand their design challenges and propose appropriate solutions.
Collaborate with R&D, Engineering, and Marketing teams to drive product improvements and solution proliferation

As we expand our presence in Israel, we're seeking a visionary System Validation Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.


Job Description
The mission of this role is to perform system validation for our highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more.

You will be part of the site located at Israel (Haifa - Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey in our company.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation.
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.


Key Responsibilities
Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments.
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence.
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments.
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners.
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient.

As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip.
Collaborate closely with Physical Design team to insure a full power integrity
Be responsible on IR architecture for timing convergence.
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM).
Understand root-cause analysis for voltage drop violations and EM risks.
Be responsible and go-to person for any IR related issues.

As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.

As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified

Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices

Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment

As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities
Execute SoC Top-level physical design and actively drive full-chip convergence.
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff.
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR).
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon.
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration.