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Were looking for an experienced SW Team Manager to join our Simulators Team, where you'll lead the design and development of our hardware simulators - functional and performance models that serve as the source of truth, drive architectural exploration and compiler optimization.
Our simulators model diverse cores within a cutting-edge SoC designed to accelerate Big Data and Database Analytics.
You will collaborate closely with hardware and software teams, contributing to co-design efforts that influence architecture, tooling, and system-level behaviour.
Responsibilities:
Lead & grow a team of experienced engineers
Develop new hardware simulators and continue evolving existing one.
Collaborate with Architecture, VLSI, and Software teams to drive co-design initiatives.
Provide insights that influence chip architecture, compiler optimization, and system-level performance.
Develop tools that drive the chip development cycle.

we are seeking a highly skilled Hardware Engineer to join our innovative team in developing cutting-edge technology solutions. The ideal candidate will have a strong background in hardware design and a passion for creating high-performance systems. Responsibilities:
* Design and implement hardware components for advanced system solutions.
* Collaborate with cross-functional teams to ensure product performance and reliability.
* Conduct testing and validation of hardware designs to meet industry standards.
* Troubleshoot and resolve hardware design issues swiftly and effectively.
* Document hardware design processes and specifications thoroughly.
* Provide Technical Support and guidance for manufacturing processes.

we are looking for forward-thinking, self-motivated engineers who thrive in fast-paced environments and "crisis times." Beyond technical excellence, successful candidates are:
Intrinsically, see the importance of every detail in "elegant solutions."
Excellent interpersonal and communication skills to work across diverse functional areas.
Schedule-driven with a desire to solve challenges that have never been solved before.
Responsibilities
Micro-Architecture & RTL: Design and implement high-quality, power-efficient RTL (Verilog/SystemVerilog) from block-level to sub-system levels.
Cross-Functional Collaboration: Partner with Architecture, Algorithm, Software, and Physical Design (PD) teams to translate product requirements into GDS-ready silicon.
Front-End Flow Management: Take ownership of "correct-by-construction" design tasks, including Synthesis, Lint, CDC/RDC (Clock/Reset Domain Crossing), and STA (Static Timing Analysis).
Verification Support: Work closely with Design Verification (DV) and Formal Verification teams to define coverage requirements, develop testbenches, and debug functional/performance issues.
Post-Silicon & Validation: Support pre-silicon emulation (FPGA, Palladium) and post-silicon validation in lab environments to ensure spec compliance.

In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.
Responsibilities
Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.

we are looking for a Hardware Lead Engineer.
As HW Lead Engineer, in the Nitro team, you will be responsible for defining Annapurna Labs Smart Network Interface Card (NIC) design, leading development and validation cycles, and bringing the product to healthy mass production.
Youll provide leadership in new technologies, bringing them to large-scale deployment, in a continuous effort to deliver a world-class customer experience. We offer a fast-paced, intellectually challenging position, where youll work with technical experts, senior leaders, covering multiple technologies. We are changing the industry, and looking for individuals who are ready for this challenge and want to reach beyond what is possible today.
Key job responsibilities:
- Define the architecture and design specifications of next generation K2 Nitro Cards.
- Own full product life cycle, engage with design partners and manufacturing sites to enable high-yield mass production.
- Lead the analysis and debugging of complex design, manufacturing, and integration challenges.
- Continuously design for process optimization to improve product quality, simplify workflows, and accelerate the Nitro card development lifecycle.

We are seeking an experienced Senior Engineering-manager with program management capabilities to help us maintained our leading cloud platforms.
Our success depends on our world-class server infrastructure;
we're handling massive scale and rapid integration of emergent technologies.
The ideal candidate will be an experienced engineer who is skilled in managing product development and pushing teams across several geographic regions using a variety of suppliers (CM, ODM/IHV).
The successful candidate will be an innovative self-starter and leader. The candidate will be familiar with the cloud computing industry and AWS offerings and will be passionate about providing the best possible customer experience at the best cost.
The candidate will have an obsession with data and precise analysis and will use these as inputs to make decisions.
Key job responsibilities:
As an Engineering-manager with program management capabilities on the Server Hardware Engineering team you will be responsible for maintaining multiple simultaneous hardware product programs in a highly cross-functional environment which includes internal customers, external vendors and technology partners.
You'll provide leadership to large scale server deployments in a continuous effort to deliver a world-class customer experience at a world-class cost point.
This is a fast-paced, intellectually challenging position, and you'll work with thought leaders in multiple technology areas.
You'll have high standards for yourself and everyone you work with, and you'll be constantly looking for ways to improve your product's performance, quality and cost.
Using data and key metrics, you will also drive and measure process improvements that enhance our operational effectiveness.
You will work independently in a dynamic, challenging, and fast-changing organization.
We're changing an industry, and we need individuals who are ready for this challenge and who want to reach beyond what is possible today.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.
Description
- Own critical block and sub-system verification of wireless SoC projects
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
- Define verification plan, create, simulate and debug test scenarios
- Drive regression and coverage analysis to ensure high quality DV
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

At High Sec Labs (HSL), a global leader in cybersecurity and secure connectivity solutions, we are looking for a talented Electronics Engineer to join our advanced development team. About the Role:
As part of our hardware group, you will take an active role in developing cutting-edge electronic products in the communication and cybersecurity domains. The role involves end-to-end board design, bring-up of new products, and integration of complex systems combining RF circuits, analog components, processors, and FPGAs.
Key Responsibilities: Design, bring-up, and validation of electronic boards and systems. Integration of RF, analog, digital, and FPGA-based circuits. Debugging, troubleshooting, and improving existing products. Close collaboration with multidisciplinary teams, including software and system engineers. Supporting the full product lifecycle from concept to production.

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

As an Expert EMIR & Power Integrity Lead, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will own from block level to full-chip the Electro-Migration and IR Drop (EMIR) methodology, analysis, and sign-off, working at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.

You will be responsible for defining power grid architectures and validating that products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes. Your work will directly impact the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Lead static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from block level to full-chip sign-off
Define and implement robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate with Physical Design teams to define optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Work closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Drive root-cause analysis for voltage drop violations and EM risks; propose and implement layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities

Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews

As the Physical Design Chip Top Expert you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SoC Top level for chips that drive the worlds largest AI clusters. As PD Top Level Lead, you will own all PD disciplines of the Chip and own the T.O GDS that meet the chip signoff Criteria (Timing, LVS, EMIR, DRC, PV etc. ) ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

SoC Top level Ownership and oversee the Chip convergence.
Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Work Closely with Package team on Bump map to Ballout taking into consideration all Signal integrity aspects