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we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies.
This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.
Key Responsibilities
The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.
Key responsibilities include:
Develop and support physical design CAD flows using industry-standard EDA tools
Build automation infrastructure for implementation, analysis, reporting, and debug
Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification
Create scripts and utilities to improve productivity, quality of results, and flow robustness
Support and enhance flows based on Synopsys Fusion Compiler
Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity
Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues.

Our HW team designs innovative end-to-end connectivity solutions for GPU servers. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. Our products are focused on delivering the most optimized power - performance communication solutions for industries like AI, ML, Cloud, Media and Entertainment as well as any other industry that can benefit from our Datastream acceleration.



What you'll be doing:

Lead Pioneering Switch System design from concept to mass production.

Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more.

Project decision maker - Technical focal point.

The position consists of product specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes.

We're seeking a talented, versatile, and highly independent Full Stack Engineer to join our engineering team. You will be in charge of end-to-end development and significantly impact both the product and technical decisions.

Responsibilities
Lead development processes from ideation to production
Develop, maintain, and imperialize the products application layer (front end & back end)
Collaborate with product, medical, and software teams across the organization
Build a customer-centric product with a deep understanding of the complex healthcare industry

We are seeking a Senior Software Architect to lead and shape the architectural vision of our SaaS healthcare platform, guide the adoption of cutting-edge AI technologies, and ensure our solutions remain scalable, secure, and future-ready. This is a hands-on, strategic leadership role that combines visionary system design, proof-of-concept development, and AI-first innovation enablement.

Responsibilities
1. Architectural Leadership

Define, communicate, and evolve the platforms architectural vision to ensure alignment with business goals.
Lead high-level design discussions and decisions for new and existing products.
Establish and maintain architectural principles, standards, and patterns across all engineering teams to ensure consistency and coherence.
Drive cloud-native architecture in AWS with a strong focus on scalability, availability, performance, and cost efficiency.
2. Innovation & Emerging Technology

Build POCs and pilots for new solutions, frameworks, and AI capabilities.
Evaluate emerging trends in AI, LLMs, MCPs, agents, and developer productivity tools, ensuring strategic adoption where relevant.
Initiate projects/features to solve widespread problems (including work with Support, DevOps, Infosec)
3. AI Tooling Evangelism

Spearhead engineering-wide adoption of AI-assisted development workflows, including developer productivity tools, code copilots, automated quality checks, and automated documentation.
Define best practices, guidelines, and governance for AI usage in development (e.g., Cursor configuration rules, prompt engineering standards).
Educate and mentor teams on effective AI utilization for engineering, product, and operational tasks, taking into account security, costs, and compliance.
4. Technical Governance & Best Practices

Overall ownership of the system scalability, COGS, and stability of the product(s)
Define standards for coding, testing, CI/CD, and monitoring.
Enforce architectural and design reviews for key initiatives.
5. Cross-functional Collaboration

Work closely with Engineering, Product, Data Science, DevOps, and Security teams to deliver well-architected solutions.
Communicate complex technical concepts to non-technical audiences, including executives and external partners.

We're looking for a motivated student who wants to take their first step into the high-tech world - and not just anywhere, but at one of the fastest-growing cybersecurity companies out there, working on some of the most interesting challenges in the industry. This is an entry-level position with real room to grow: you'll get hands-on training, mentorship, and the chance to develop into a full Technical Support Engineer role over time.
Responsibilities:
Provide accurate and timely support via Slack, chat, or email to help troubleshoot and resolve customer issues.
Learn to diagnose technical problems and escalate complex issues to R&D or Product when needed.
Build strong relationships with customers and maintain a professional, supportive tone.
Help create and update support documentation, and log interactions in the support system.
Continuously build your technical skills through ongoing training and mentorship.

we are looking for a Technical Support Engineer
Responsibilities
Resolve customer issues daily, ensuring timely responses and high levels of customer satisfaction
Proactively manage the day-to-day resolution of customer issues in a timely (SLA) manner and maintain their high satisfaction
Contribute to methodologies, best practices, and techniques to improve our support process
Build and contribute to Navinas technical support knowledge base.
Work closely with R&D, Product, Customer Success, and our Medical team for complex problem-solving and time-sensitive escalations.

We are now looking for a Power Optimization and Analysis Engineer! We prides ourselves on having energy-efficient products. We believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. As part of the u/arch team in the Switch group, you will be responsible for analyzing full chip and unit-level power data and driving the FE/BE ASIC teams to improve their units power efficiency; you will be responsible for researching, developing, and deploying methodologies to help our products become more energy efficient. Key responsibilities include developing techniques to model, analyze, and reduce power consumption of our Switches product line.

As a member of Switch u/arch Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for our next generation switches. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.

What You'll Be Doing:

Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.

Develop and share best practices for performing pre-silicon power analysis.

Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.

Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.

Select and run a wide variety of workloads for power analysis.

Prototype new architectural features in Verilog and power analysis.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.
You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.
Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip
Collaborate closely with Physical Design team to insure a full power integrity
Be responsible on IR architecture for timing convergence
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)
Understand root-cause analysis for voltage drop violations and EM risks
Be responsible and go-to person for any IR related issues.

Required Sales Development Representative (Tel Aviv)
The Opportunity:
This is not a traditional Sales Development Representative role.
SDRs are deeply embedded in the sales process and take ownership well beyond initial outreach. You will not only generate and qualify pipeline, but also help progress opportunities through discovery and into the scoping stage, working closely with Account Executives to shape early-stage deals and influence how customers evaluate us.
This is a high-impact, high-visibility role for someone who wants more than activity targets, someone who wants ownership, commercial exposure, and a fast track into a closing or strategic sales role.
You will play a critical part in driving our growth, engaging with security, cloud, DevOps, and engineering leaders at some of the most forward-thinking organisations in the world.
What Youll Do:
Research, identify, and engage prospective customers across target accounts and territories.
Build and maintain a strong outbound pipeline through cold calling, email outreach, LinkedIn engagement, and industry events.
Develop a strong understanding of our platform, value proposition, and competitive positioning.
Run structured discovery conversations to understand technical and business challenges in cloud security environments.
Progress opportunities beyond initial qualification and actively support Account Executives through early-stage discovery and scoping conversations.
Navigate complex enterprise organisations and engage stakeholders across.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.
Key Responsibilities
Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient.

We are now looking for a verification engineer for our FC Switch Silicon team. As a FullChip verification Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a FC verification team within the Switch silicon.

Dynamic verification environments planning for units infrastructures and system level.

Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

Responsible to drive the FullChip verification execution, including staging plan of the projects and deliveries.

Our Networking System Product Engineering group is looking for an excellent Software Engineer. The position requires an understanding of HW and SW to provide stable, efficient, smoothly running production tests, to enable high availability, while ensuring the quality of the products being shipped to customers. You will lead the development of our products and raise the bar of the software development quality in the group. We have crafted a team of extraordinary people, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.

What youll be doing: 

Design and develop automated tests for networking Switches and Adapters while working closely with the HW, ASIC, and SW Engineering teams to achieve a reliable test with high coverage.

Exposed to various aspects of design, DFT, and test of our next-generation network products.

Take a significant part in the definition and development of tests from the development level to the final test of Network-Systems.

Utilize test suites to find, debug and resolve problems with production process.

Ability to drive projects to full execution in time and working under pressure of schedule and multi project environment.

Supporting and fixing bugs of existing code. Supporting production lines for: deployments, patches, maintenance.

Test Verification and Validation (both HW and SW). Troubleshooting and streamlining/optimizing our testing procedures.