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We are looking for a highly skilled RF Test Automation Developer to join our R&D Integration Automation team.

This role is focused on designing, developing, and maintaining advanced automation solutions across unit, integration, system, and end-to-end testing levels.

The ideal candidate is a hands-on developer with strong expertise in Python and Pytest, experienced in building and executing automated tests, and comfortable working with modern CI/CD pipelines and automation tools.

The Senior Developer will act as a technical mentor and key contributor, ensuring best practices are followed and test automation is seamlessly embedded into the development lifecycle.

Knowledge of RF systems is a strong plus.

Key Responsibilities:
Develop and maintain automated RF test development tools using Python and other relevant programming languages.
Configure, calibrate, and operate RF test equipment such as Vector Signal Generators (VSGs), Spectrum Analyzers (SAs), and related instruments.
Create and validate RF test setups for performance validation, debug, and system characterization.
Analyze test results, generate comprehensive reports, and present findings to cross-functional teams.
Collaborate with hardware and software engineers to integrate automated RF testing into the product development cycle.
Stay current with emerging RF technologies and testing methodologies, proposing and implementing improvements to existing test processes.
Contribute to the development of RF testing strategies aligned with R&D goals and product roadmaps.
Research and introduce innovative RF automation tools, frameworks, and workflows aligned with R&D goals.

We are seeking a highly skilled Senior Communication PHY Algorithms Engineer.
This senior role is focused on the end-to-end research, design, and implementation of digital receivers for proprietary drone communication signals.
Responsibilities:
Mathematically characterize complex communication and signal detection problems. Analyze and assess design trade-offs based on both performance metrics and implementation complexity.
Develop and maintain simulations using MATLAB and Python.
Design digital receiver modules to be implemented either by FPGA of SW.
Implement features directly in SW or technically lead and verify the FPGA implementation efforts of the FPGA engineer.
Accompany the integration process of the feature until its end-to-end operation.

The Opportunity We are starting a new ML/AI organization directly reporting to the CTO, to pioneer next-generation capabilities for our industry-leading defense systems. As a Founding ML-Engineering Lead, you will be the technical cornerstone of this initiative. This is a high-impact role designed for a practitioner who seeks total technical ownership of the machine learning lifecycle. You will be responsible for taking novel AI projects from initial concept through data collection, design, implementation, and evaluation, all the way to deployment.

The Technical Challenge Our ML initiatives span a diverse technical landscape. You will lead projects that range from field-oriented applications, where high accuracy and reliability are paramount, to research-oriented tools and agentic workflows designed to enhance our R&D capabilities and accelerate complex data analysis. Working in deep collaboration with our R&D teams, you will leverage unique, proprietary data to solve problems at the forefront of the counter-drone industry.
What You Will Do:
End-to-End Ownership: Lead the full technical execution of ML projects, ensuring every stage-from data acquisition to deployment-meets our rigorous standards.
R&D Collaboration: Partner closely with R&D departments to design data collection strategies and integrate ML-based tools and agents into their specialized workflows.
Versatile Implementation: Develop models and intelligent systems for a variety of use cases, ranging from real-time field performance to autonomous research-support tools.
Technical Authority: Act as a founding voice for ML implementation and strategy within the CTOs office.

Role responsibilities:
Final tests technician (Hands-on) in Production line.
Manage HW testing in production, Line setup, Calibration and Maintenance.
Deep HW knowledge in RF & Digital.
Functional testing of electronic circuits according to specifications.
Overall responsibility for debug & analysis in boards & System level.
Responsibility repair, analysis and documentation.
ATE stations technical support.

our companys innovative processors are designed into the advanced cellular systems of most tear-1 carriers .
We are looking for an experienced and creative Verification Engineer to join our Processor Verification Team.
In this role, you will be responsible for verifying the core units of our next-generation processors. You will work closely with the architecture and design teams to ensure functional correctness through advanced verification methodologies, taking ownership of verification environments from planning to coverage closure.

We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
our Impact
As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence.

About the group:
We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

Will drive the implementation of autonomous core power management for best performance and power efficacy.
The Power expert will take charge in understanding business-units (customers) needs, and translate them to CPU core solution.
This expert will utilize his power management experience to deliver world-class power efficient HW-SW solutions for Huawei products.
Responsibilities
Responsible for bringing Huawei CPU to a leading position in Performance-Power efficiency.

We are looking for an experienced and creative AI processor VLSI Architect to architect and model the core of our next generation processors.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.