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We are looking for a Supply & Demand Planner to join our Global Planning Team, part of our Customer Delivery organization
This team sits at the intersection ofOperations and Customer Success
ensuring that every planning action ultimately supports on-time, high-quality delivery to our customers
You will be responsible for the entire planning process, from demand forecasting through to supply execution. This is not a support-level role; it is a cross-functional, strategic position focused on balancing availability, inventory, cost, and service level.
What will you do?
Own global demand forecasting for spare parts and material, based on data, trends, and input from business units.
Translate demand into actionable supply plans using Oracle Cloud ERP
Partner with Procurement, Engineering, Warehouse, and Customer Success teams to resolve shortages, expedite supply, and implement changes (ECOs, NPIs, phase-outs).
Collaborate cross-functionally to support product transitions and customer delivery KPIs.
Monitor and improve key planning metrics: Forecast Accuracy, Inventory Turns, Plan vs. Actual, Delivery SLAs.
Analyze supply risks and continuously improve planning tools and processes.

Execute comprehensive testing of AI datacenter networking solutions, focusing on SONiC-based systems, smart NIC integration, and high-performance networking for AI workloads.
Key Responsibilities:
Design large scale testing topologies with GPU/Traffic Generators and execute test cases for SONiC/our company network operating system functionality.
Validate smart NIC performance and integration with SONiC datapath
Perform functional, performance, and stress testing of AI networking scenarios
Develop automated test scripts for regression testing and continuous validation
Execute interoperability testing between different hardware vendors and software versions
Validate RDMA, high-speed Ethernet performance for AI workloads
Test failover scenarios and network resilience under various failure conditions
Document test results, file detailed bug reports, and track issue resolution
Collaborate with development teams to reproduce and isolate defects
Participate in customer proof-of-concept testing and field issue reproduction.

Kendago is a global leader in Direct-to-Consumer (D2C) digital marketing and advertising. We provide brands with a comprehensive suite of services, including proprietary AdTech-backed PPC, creative production, digital marketing expertise, and data-backed CRO optimization. We help our clients grow into world leaders by combining our unique approach to PPC with a focus on brand development, funnel optimization, and ad creativity. We are looking for an highly experienced Senior Full-Stack Software Engineer to join our core team. In this role, you will be a key technical pillar, responsible for driving the development of our most mission-critical features from concept to production. You will blend deep technical hands-on execution with high-level architectural design , ensuring our systems are robust, scalable, and built for performance. This is a hybrid position, including two to three work-from-home days per week , with flexibility based on team and individual needs. Our Office is located in Kiryat Ono.

Responsibilities:
Technical Leadership & Execution: Lead the end-to-end development of core features, maintaining a high standard of hands-on coding while overseeing the technical lifecycle. System Architecture: Design and build complex, scalable, and high-performance distributed systems. Collaboration: Work closely with Product Managers, Designers, and cross-functional teams to translate product vision into actionable technical requirements. Continuous Improvement: Drive the evolution of our development processes, system infrastructure, and overall code quality. Mentorship: Act as a technical mentor for team members, conducting code reviews and establishing engineering Best Practices.

Biz Dev:
R&D

Remote/Part time:
Hybrid

We are seeking a capable and experienced Algorithm engineer to join our R&D team. The engineer will be part of a team responsible for the core autonomy parts of the product responsible for developing the foundational algorithms that guide our autonomous vehicles. This role is a part of the group that oversees Motion Planning, Decision-Making, Localization, and Control, blending traditional robotics with state-of-the-art AI to solve the most challenging problems in autonomous driving. This is an opportunity to architect and deliver the core autonomy stack for a scalable, mapless L3-L4 system. You will work on cutting-edge algorithms, including Agentic AI and large-scale models, and see your innovations deployed on public roads in our global fleet of cars and buses. Responsibilities Be part of the development of four key domains: Motion Planning and Decision-Making: Oversee the trajectory planner and the decision-making module that sets the context for vehicle behavior. Localization: Guide the development of high-frequency, high-accuracy vehicle state estimation using advanced sensor fusion algorithms. Control: Supervise the design and implementation of the vehicle's lateral and longitudinal controllers. Drive innovation by integrating state-of-the-art (SOTA) methodologies, including Agentic AI, vision language models (VLMs), transformers, multi-agent prediction, trajectory optimization, uncertainty management, and safety-aware algorithms.
* Be part of a group involving multiple engineers, from initial research and prototyping to robust deployment and validation.
* Be part of a group in charge of complex data pipelines, from collection and annotation to model training and evaluation.

At Lumissil, we are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, Lumissil is the place to develop your skills, innovate, and grow your career. Why join us?
* Work on cutting-edge automotive projects
* Learn from a talented and supportive team
* Gain exposure to real-world automotive challenges
* Grow your career in a collaborative and inspiring environment If you’re ready to take the next step in your career and be part of something meaningful, we’d love to meet you! About The Position: As a Junior ASIC Design Engineer at Lumissil, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where you’ll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions
* Support and learn from real emulation platforms used in production-grade designs
* Contribute to RTL implementation and gain practical experience in design flows
* Assist with verification and backend (BE) activities, learning industry best practices
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

Design, implement, and test a state-of-the-art optimizing compiler for Cisco Silicon One
Evaluate and optimize code performance, including debugging, code generation improvements, and pipeline analysis
Develop, optimize, and enhance the compiler backend to fully leverage cutting-edge hardware capabilities
Solve complex resource management challenges across hardware pipelines
Design and implement new P4 language features that empower network application developers
Build and maintain the compiler toolchain for custom networking applications
Contribute to libraries, analysis tools, and supporting infrastructure
Collaborate with cross-functional hardware and software teams
Work closely with ASIC engineers on next-generation IC design, influencing hardware through compiler insights prior to tape-out

We push the boundaries of technology, developing innovative DFT solutions that drive industry-leading programmability, scalability, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation.

Your Impact

As an Experienced DFT Engineer, you will:

Own and drive DFT execution across the full product lifecycle, from pre-silicon design through post-silicon debug and production qualification.

Define and align DFT architecture and strategy in close collaboration with chip architects, design, and verification teams.

Oversee and contribute hands-on to the implementation of DFT features, including ATPG, scan insertion and compression, and memory BIST.

Lead silicon debug activities and root-cause analysis, driving corrective actions to improve yield, reliability, and test quality.

Establish, standardize, and evolve DFT methodologies and best practices across projects.

As a key member of the team, you will be responsible for developing a state-of-the-art functional simulator for the family of devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.

In this role, you will:
Design, implement, and validate components of the behavioral model for SiliconOne devices
Collaborate with ASIC Architecture, Software, and Hardware teams to ensure alignment and seamless integration
Apply engineering best practices for code quality, performance, testing, and documentation
Troubleshoot and resolve complex technical issues
Contribute to defining best practices and methodologies for model development, validation, and integration

Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies

We are seeking a motivated Software Engineer to join our team and contribute to the development of a functional simulator for the family of switching and routing ASIC devices. This simulator plays a vital role in accelerating our product development process and ensuring high-quality hardware solutions.

In this role, you will:
Work under the guidance of senior engineers to help implement and maintain components of the simulator based on architecture specifications.
Collaborate with the ASIC Architecture, Software, and Hardware teams to understand requirements and support their use of the simulator as a reference for development.
Participate in troubleshooting, testing, and validating simulator functionalities.
Learn and apply industry best practices in model development and integration.

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Collaborate closely with the ASIC Architecture team to implement an accurate and efficient software model based on the architecture specifications.

Partner with both Software and Hardware design teams, providing support as they use the simulator as the golden reference for hardware implementation.

Ensure the simulator meets the highest standards of performance, reliability, and usability.

Contribute to defining best practices and methodologies for model development, validation, and integration. 

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.