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looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. 
what you will be doing:
join tel aviv group, working in a combined design and verification team which develops phy layer ip within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, fw and post-silicon validation.

we are now looking for a senior chip design engineer to join our switch silicon team. as a chip design engineer networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! 
what you'll be doing:
work in a design/verification team which develops core units within the switch silicon.
micro-architecture of rtl verification environments planning for units and modules.
design rtl of units/blocks according to arch. specifications under challenging constraints with high orientation to power, area, and performance.
rtl synthesis, timing, supporting verification, and silicon post to activities.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw.

we are now looking for a best-in-class Verification engineer to join our outstanding gpu-networking silicon engineering team. as a dv engineer at gpu-networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry - gpu super-chip. 
what youll be doing:
work in a dv (design verification) team that has a global responsibility over deliverable units and clusters to the silicon gpu
integrations and full-chip models
verification of chip blocks/entities according to specifications under challenging constraints
ramp-up and run dv tasks on emulation platform

we are seeking a highly motivated high-performance system architect to join our team of experts and help shape the future of high-performance and ml / ai computing. our next-generation nvl systems will be at the forefront of connecting and powering the world's most advanced compute clusters, which would be used to train the most advanced ai models such as gpt and deepseek. as a high-performance system architect at nvidia, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.
what youll be doing:
define the nvl system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
research various of solutions to enable the next large-scale-high-performance computing clusters. the position spans over various layers from algorithms, software, firmware, and hw.
collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

we are looking for a senior chip design Verification engineer for developing the next generation dft technologies.
as a senior chip design Verification engineer in the dft team , you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

our company is looking for an experienced dft design engineer to join the dft design team and develop the next generation dft technologies.
as a design engineer in the dft design team at our company, you will participate in definition and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and sophisticated products, our dft solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for defining, coding and integrating sophisticated dft components into various projects and using state-of-the-art technologies.
as a member of our dft design team, you will participate in defining various dft features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

as a Senior Software Architect in the gpu networking architecture team, you will define software defined networking architectural solutions. you'll also be part of a team of specialists who span across numerous technological fields related to the modern data center, such as distributed ai and deep learning systems, networking operating systems, virtualization, Storage, and more.
what youll be doing:
define system and software architecture for software defined networking (sdn) of ground breaking emerging ai networks which involves innovative software and hardware.
be an active member in setting the use-cases and metrics for monitoring complex high-speed networks control-plane.
work closely with various groups within nvidia to bring ai network technologies to reality, including gpu and switch hw and sw teams, product as well as fellow architects.

we are now looking for a senior hpc site reliability engineer to join our mission and continue improving our hpc infrastructure. a meaningful part of nvidias strength is our unique and advanced development tools and environments that enable our incredible pace of innovation. we are looking for architects to help us evolve the way our private compute cloud is architected and optimized. 
what you will be doing: 
provide leadership in the design and implementation of our large-scale compute cloud that enables the world's top chip modelers, designers, and deep learning experts to invent groundbreaking technology.
identify architectural changes or completely innovative approaches in our cloud architecture and design. 
help with strategic challenges we encounter, including: effective resource utilization in a heterogeneous compute environment, evolving our private/public cloud strategy, capacity modeling, and planning for multi-year growth and scaling across our global computing environment!

we are currently seeking a power integrity engineer. you will collaborate closely with our teams in the usa and india, drawing on extensive knowledge, technologies, and tools. as part of our team, you will contribute to the development of our ethernet switch system product line, supporting the process from concept through design, implementation, verification, and release to customers. if you enjoy working with talented individuals to achieve ambitious goals, nvidia could be the ideal place for you. our team is dynamic, working with cutting-edge and unique technology. if youre someone who thrives on challenges, we invite you to join this diverse team and make a significant impact!
what you'll be doing:
ensuring robust power integrity in physical design to optimize power delivery
design and optimize physical design solutions for power integrity. 
perform power integrity analysis and mitigation. 
focal point for pi for partitions owners.
collaborate with hardware and design teams on power delivery strategies.
utilize tools and flow in advance technology to meet project development

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. we make outstanding artificial intelligence happen and accelerate open-ais chat-gpt, for example. we believe in our people and products and seek excellent people to join us!
we're looking for a hardware u/architect for our switch division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our next generation switch product lines performance, both ethernet and infiniband. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system requirement and help define the por of our switch product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand ethernet, infiniband and nvlink protocols.

looking for an hpc and ai data center engineer to join the networking cloud solutions hpc/ai infrastructure team. we are focused on building supercomputers and hpc clusters based on groundbreaking technologies. we are looking for a lab manager, be a key player to the most exciting computing hardware and software to contribute to the latest breakthroughs in artificial intelligence and gpu computing. take part of building large-scale compute and deep learning software and hardware platforms, work together and support many scientific researchers, developers, and customers to craft improved workflows and develop new, leading differentiated solutions.
what you will be doing:
plan and build complex cluster and supercomputers in various of data center and labs
rack stack and cable management to ensure efficient use of space and easy maintenance
ensure data centers and labs power and cooling efficiency while optimizing rack space utilization
data centers and labs daily operation and support
installations for variety of infrastructure and solutions - cloud, vms, Storage, network, hpc and ai
perform troubleshooting - network, optic cabling, bare metal, operating system.
support research & development activities

join our growing software architecture research team. the ideal candidate will be conducting cutting-edge research at the intersection of networking, security, and communications, and working alongside top experts in these fields. with incredible resources in networking, you will be able to impact, contribute and advance these domains for scalable accelerated computing. topics include but are not limited to remote direct memory access, hardware offloading and hardware acceleration, distributed accelerator networks, ai for networking and security, Storage management, cryptography accelerators and architecture. with its unique open culture, nvidia is one of the best industry labs to do accelerated computing research.
 
what youll be doing:
develop novel hw architecture models
simulations ranging from specific components to complete data center environments
develop sdks for novel hw capabilities
designing and implementing services, runtime systems, and applications over sdk
evaluate and optimize application performance
partner and collaborate with other forward-thinking team members and external researchers
participate and speak at conferences and events
work with intelligent networking machines powered by ai systems that can learn, reason and interact with other network components

as a senior architect in the advanced development team, you will explore technological challenges on accelerate networking and building ai data centers. research new transport functions and semantics for optimizing ai workloads. you will also be leading architectural and development efforts across numerous technological fields, related to the modern data center, such as distributed ai and deep learning solutions, data analytics, high performance computing (hpc), software defined networking (sdn), virtualization, Storage, and more.
what youll be doing:
enhance gpu networking offerings for accelerating ai workloads, such as dynamo or nvidia nixl.
identify and evaluate new technologies, innovations and partner relationships for alignment with our technology roadmap and business value.
lead architecture and design of such technologies.
lead proof-of-concept development to evaluate and drive such technologies.