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DustPhotonics develops cutting-edge technology in Silicon Photonics, which is revolutionizing connectivity and communication in data centers. Silicon photonics is becoming a standard technology used for high-performance systems, solving challenges related to performance, integration, power, and cost. This technology is also growing rapidly in other markets, such as healthcare, LIDARs, and other sensors. At Dustphotonics, we are committed to solving difficult problems in a smart and simple way, thinking outside the box, leveraging the knowledge and know-how of our team members, and working together to create magic. Our company culture is characterized by accountability for our ethics and for being fair to every employee, customer, supplier, and partner. We believe in working hard and having fun on the way to success. We welcome you to join our team – apply for your next career opportunity with us! We are looking for an Electrical Engineer to join our Wafer-Level Testing (WLT) team. In this role, you will work on both development and production wafers of Photonic Integrated Circuits (PICs) , performing testing, data analysis and automation to improve device performance, design and yield.

Responsibilities:

* Perform wafer-level testing (WLT) on PIC development and production wafers.
* Develop, maintain, and enhance Python-based test and data analysis scripts.
* Automate test processes and improve data collection and analysis workflows.
* Analyze electrical and optical test data to extract key performance insights.
* Collaborate closely with process, packaging, and design teams to optimize device performance and yield.

Join our team in a pivotal role where you'll own the entire IP-level netlist generation and timing convergence journey from synthesis to sign-off.
You'll drive synthesis, UPF power intent, scan insertion, and external IP integration while architecting timing constraints for both standard and complex custom designs that ensure sign-off quality from day one.
Working at the intersection of multiple disciplines, you'll partner closely with RTL designers to deeply understand design intent and clock architecture, collaborate with CAD teams to shape and optimize cutting-edge flows, and team with Physical Design engineers to achieve flawless timing sign-off.
We're seeking an innovative thinker who brings fresh perspectives to timing analysis methodologies and proactively identifies and resolves timing challenges to eliminate pessimism and accelerate convergence, ultimately making their mark on next-generation chip design.

We are looking for a FE CAD Engineer.
Description:
Develop and maintain internal EDA tools and frameworks for RTL assembly and connectivity checking.
Implement efficient algorithms for hierarchical RTL construction, module binding, and interface consistency across complex SoCs.
Build intelligent connectivity, visualization, and debug utilities.
Collaborate with front-end design, DFT, and integration teams to align methodologies and define tool requirements.
Drive automation and performance improvements, including runtime optimization and scalability across large designs.
Support adoption, documentation, and user training for internal design teams.

We are looking for a Director of Software Technical Program Management that will be responsible for Software programs and projects that are part of our solutions. We have been defining computer graphics, PC gaming, and accelerated computing for more than 25 years.

As a Director of Technical Program Managers in the Software Networking Architecture team, you will lead and grow a program management team within a rapidly expanding architecture group, driving accelerated development of early-stage capabilities. Youll join a team of specialists spanning multiple technological domains of the modern data center including distributed AI and deep learning systems, networking operating systems, virtualization, storage, and more.

What you'll be doing:

Lead and Develop Project Managers: Manage a team of project managers driving networking software programs for our next-generation AI data centers during the early development phase, from project initiation until features are part of the engineering Plan of Record (POR).

Define and Improve Processes: Identify gaps in current architecture practices and establish program management methodologies for planning, prioritization, and KPI alignment.

Act as the lead Technical Program Manager for one of the core networking software technologies, driving the program from initiation through integration into the engineering Plan of Record (POR).

Foster Cross-Functional Collaboration: Act as a bridge across teams, programs, business units, and functions to align efforts, anticipate challenges, and ensure smooth execution.

Oversee the Big Picture: Manage technical and business dependencies, facilitating scalable communication, and enabling coordinated execution across the organization to ensure consistency with company strategy, commitments, and goals.

Be Results-Oriented and Strategic: Driving systematic planning, tracking progress, and ensuring accountability and visibility to executives.

Identify risks, gaps, and bottlenecks in time, and find resolution with technical leaders and project management.

We are looking for a Senior Technical Program Manager that will be responsible for Software programs and projects that are part of our solutions. We have been defining computer graphics, PC gaming, and accelerated computing for more than 25 years. As a Senior technical program manager in the Software Networking Architecture team, you will be a pivotable function in managing the software programs in the phase between initiation till its ready to be added to engineering as plan of record (POR).

You'll be part of a team of specialists who span across numerous technological fields related to the modern data center, such as distributed AI and deep learning systems, Networking Operating Systems, Virtualization, Storage, and more.

What you'll be doing:

You will manage networking software programs for our next generation AI Data centers during the early development phase (from initiation till feature is part of engineering plan of record (POR).

Responsible to coordinate between all project stakeholders in IL and around the world.

Develop and execute feature planning and prioritization of perception capabilities to meet the software programs' needs.

Identify risks, gaps, and bottlenecks in time, and find resolution with technical leaders and project management.

Work with product managers, architects, program management, and engineering team to ensure consistency with company strategy, commitments, and goals.

We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.