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Define and implement solutions for complex design, integration and verification problems using in house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Be involved in project development and convergence with the highest quality, work on issues as they arise through design and implementation.
Connect between RTL design, physical design, DFT, external IPs and System on a Chip (SoC) while maintaining project priorities.
Maintain project infrastructure and stability.

Lead architectural definition of CPU core designs, facilitate and make final decisions.
Participate in and influence the building of processor performance analysis infrastructure.
Influence the development of architectural models with varying configurations across product categories.
Perform Performance, Power, Area (PPA) trade-off analysis for architecture and microarchitecture features, communicate analysis results in both qualitative and quantitative fashion to support decisions.

Develop methodology of SoC roll up of power reduction, projection, configuration, test plan and tools.
Work intact with Architecture, Frontend and Backend teams driving power reduction features (both logic and circuit).
Support power delivery and packaging teams with simulations and scenario definitions.
Work intact with Architecture and DV to define power scenarios and tests, debug, and integrate into the flow.
Track power goals are met throughout execution.

We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Design, develop, test, deploy, maintain, and improve CPU software modeling and other software tools.
Manage individual project priorities, deadlines, and deliverables.
Collaborate with hardware and software CPU architecture teams, SOC performance modeling team, and other Google Software teams.

As a Technical Program Manager for Silicon Development, you will use your technical and management experience to lead the development and execution of complex, multidisciplinary SoC projects. You will plan programs and manage their execution from early concepts through development to tape-out and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan, coordinate, and deliver custom silicon products.
Assess complexity and scope out the project, generate task lists, build a project timeline and work with the teams to make it into reality.
Lead the data-driven schedules and milestones, track the progress, proactively identify potential future issues, and identify mitigations with the team leaders.
Drive technical, budgetary, and schedule trade-off discussions with cross-functional teams.
Manage project execution and issues through design, development, test, manufacturing, deployment and sustaining activities for silicon and hardware products.

Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.

Work with partner teams to provide the compute, storage and methodology needs of the chip design, verification and physical design teams.
Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies.
Design and implement CAD tools, solutions and methodologies for ASIC development.
Extend the capabilities of third-party tools through their dedicated APIs.
Provide documentation, training, and support to increase end user productivity.

Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools on Emulation and/or FPGA platforms.
Lead the debugging and resolution of complex silicon issues, collaborating with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.
Build and mentor a high-performing team of silicon validation engineers, fostering a culture of collaboration, innovation, and technical excellence.

Plan the verification of digital design blocks by understanding the design specification, and interacting with design engineers to identify important verification scenarios.
Lead a team of chip engineers. Plan tasks, allocate people, and hold verification design/code reviews.
Perform code development for critical verification features and capabilities.
Work with system, software, design, and physical implementation stakeholders to make technical decisions and represent project status throughout the development process.
Lead design verification efforts and work with external and internal partners.

We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the System on a Chip (SoC)/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and Application-specific integrated circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.

As a member of the Package Design Team, you will:
Lead package design tasks, being responsible for planning, coordinating with partners, and driving schedules from start to finish.
Optimize package pinouts, stack-ups, placements, power distribution, and high-speed routing while balancing functional needs, manufacturing constraints, and performance considerations.
Collaborate with silicon floor plan, signal integrity (SI), and power integrity (PI) teams to ensure design quality and efficiency.
Work closely with layout editors to implement the package design, ensuring alignment with high-speed signal and functional interface requirements.
Enhance design methodologies and procedures, collaborating with vendors and developers to improve product quality and design efficiency.

You'll be joining our Physical Design team within our Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.

As part of our team, youll contribute to the development of our next-generation network devices. Our team operates in a startup-like environment within a stable and leading corporation.

We are looking for a System Project Team Lead to lead Novas system development.

What you will be doing:
Responsible for the entire projects system performance.
Be the system go-to person on all things technical, a technical expert knowledgeable with the system operation, measurement, performance, and troubleshooting.
Design the system architecture and high-level design and technical requirements - Details of the system, sub-system, and module requirements.
Lead the development activities and technical reviews throughout the products life cycle (SRR, PDR, CDR, and FDR). Lead other technical design reviews as needed.
Plan, manage, monitor, and lead the project to ensure delivery of the product within the required specifications, on time, and within the allocated budget.
Key contact for any in-bound topics, interfacing with the matrix organization
Interface with the product manager on any outbound topics (towards the customer).
Maintain a risk management and mitigation plan.
Ensure the product meets the performance, quality, and reliability requirements.
Responsible for project task assignments, follow-up, and alignment with interfacing development groups, service, and production.
Responsible for leading the technical aspects of the beta activity.

We are looking for a System Physicist- M.Sc. Student to be responsible for a novel product throughout its life cycle from the development stage to installation and support at customer sites, as part of a team.

The student system engineer will practice innovative and critical thinking together with methodological and precise scientific investigation, both broad and in-depth investigation of complex multi-disciplinary systems acquiring strong insight of the physics and algorithms defining its performance.

What you will be doing:
Theoretical and experimental study of new system methods and algorithms to support state-of-the-art solutions.
Define and oversee the implementation of your solutions.
Hands on tool experiments and testing in clean-room environment.
Service and production guidance and support on challenging topics.
Collaboration and system lead with HW and SW engineers.
Data and statistical analysis.
Advanced logic and sequence design.
Algorithm development.
Performance and critical behavior testing and design.
Developing practical solutions and methods for critical challenges.
Conduct lab and on-site system diagnostics, troubleshooting, and problem-solving. Tasks include root-cause analysis, mitigation plans, implementing robust system calibration methods, and product transfer to manufacturing.
Intensive interface with diverse disciplines: physics, optics, algorithms, mechanics, electronics, and software.
Transform customers high-level requirements into concrete technical specifications and design.