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in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, system testing, and verification closure. you will verify digital designs, collaborate with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner cases and expose all types of bugs. you will manage the full lifecycle of verification which can range from verification planning, TEST execution, or collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog or formally verify designs with strategic value add (sva) and industry-leading formal tools.
identify and write all types of coverage measures for stimulus and corner cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, system testing, and drive verification closure. you will verify digital designs, collaborate closely with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. you will manage the full life-cycle of verification, which can range from verification planning, TEST execution, to collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog and uvm, or formally verify designs with sva and industry leading formal tools.
identify and write all types of coverage measures for corner-cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.

as a cpu design Verification engineer, you will work as part of a research and development team building verification components, constrained-random testing, system testing, and verification closure.
as part of our server chip design team, you will verify complex digital designs. you will collaborate with design and Verification engineers in active projects and perform verification. you will be responsible for the full lifecycle of verification which can range from verification planning, TEST execution, or collecting and closing coverage.behind everything our users see online is the architecture built by the technical infrastructure team to keep it running. from developing and maintaining our data centers to building the next generation of google platforms, we make product portfolio possible. we're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. we keep our networks up and running, ensuring our users have the best and fastest experience possible.
responsibilities
plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog or formally verify designs with systemverilog assertions (sva) and industry leading formal tools.
identify and write all types of coverage measures for stimulus and corner-cases.
debug tests with design engineers to deliver functionally correct design blocks.
apply close coverage measures to identify verification holes and to show progress towards tape-out.

about the job
the growth and notifications (gant) data science team's mission is to deliver the best of google's products to our users by enabling high-quality notifications and driving growth across the ecosystem. we are a team of data scientists and analysts who work to embed a deep empirical understanding of user behavior into the product development lifecycle. this enables our product partners to take smarter risks and build more engaging, high-quality experiences that drive sustainable growth.we are part of the broader ecosystem growth (eg) data science team within google identity and engagement (gie). our work is pivotal in increasing the number of users who experience the full value of google.this is an exciting opportunity to join a team that is at the forefront of driving user engagement and ecosystem growth at google.
responsibilities
lead large-scale data analysis and novel modeling approaches to create a deep understanding of user behavior with notifications and proactive agentic experiences.
partner with product, engineering, and UX research to define and develop novel evaluation metrics, validation methodologies, and experimentation frameworks for proactive quality models and ai-driven notification agents.
provide analytical thought leadership and advanced statistical expertise on user journeys, engagement models, and long-term causal effects across the gie and google ecosystem.
translate complex findings into actionable product recommendations, effectively presenting to cross-functional stakeholders at all levels to influence the product roadmap.
define, implement, and own key metrics to measure the quality, impact, and value of notifications and user-state models.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a cpu workload analysis researcher within our company cloud's msca organization, you will be integral to developing silicon solutions powering our company's direct-to-consumer products. you will join a research and development team focused on analyzing and profiling workloads requirements within the company cloud environment. your role will involve conducting in-depth research on cpu optimization, feature development, and ml usages over compute platforms, contributing to identifying key areas of investment and future opportunities. this role offers a unique opportunity to perform groundbreaking research with a significant impact on both research methodologies and industry products, within the server chip architecture team. your work will directly influence the next generation of hardware experiences for millions of our company users and cloud customers.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
plan and execute detailed analysis of cpu workloads within the company cloud infrastructure, analyze trends and map future requirements.
collaborate closely with architecture and modeling owners to understand design specifications and identify critical scenarios related to cpu performance and efficiency.
develop and implement custom workload generation tools and methodologies to simulate real-world usage patterns on our company cloud platforms.
analyze the impact of Machine Learning applications on cpu usage, identifying opportunities for optimization and feature enhancements.
lead the investigation and development of metrics to measure cpu performance and efficiency, presenting findings to stakeholders and contributing to strategic decisions.

about the job
when leading companies choose our company cloud, it's a huge win for spreading the power of cloud computing globally. once educational institutions, government agencies, and other businesses sign on to use our company cloud products, you come in to facilitate making their work more productive, mobile, and collaborative. you listen and deliver what is most helpful for the customer. you assist fellow sales our company by problem-solving key technical issues for our customers. you liaise with the Product Marketing management and engineering teams to stay on top of industry trends and devise enhancements to our company cloud products.
as a customer engineer, you will work with technical business teams as a Machine Learning subject matter expert to differentiate our company cloud to our customers. you will help prospective customers and partners understand the power of our company cloud, explain technical features, help customers design architectures, and problem-solve any roadblocks. you will also have the opportunity to help customers to leverage specialized Machine Learning (ml) hardware developed by our company , called tensor processing unit (tpu). you will work with customers and product development to shape the future of the platform.our company cloud accelerates every organizations ability to digitally transform its business and industry. we deliver enterprise-grade solutions that leverage our companys cutting-edge technology, and tools that help developers build more sustainably. customers in more than 200 countries and territories turn to our company cloud as their trusted partner to enable growth and solve their most critical business problems.
responsibilities
work with the team to identify business opportunities, understand key customer technical objections, and develop the strategy to resolve technical blockers.
provide Machine Learning (ml) expertise to support relationships with customers, including product and solution briefings, proof-of-concept work, and partnering with product management to find solutions.
work with customers to demonstrate our company cloud product integrations in customer/partner environments.
recommend integration strategies, enterprise architectures, platforms, and application infrastructure to implement a complete solution using best practices on our company cloud.
travel to customer sites, conferences, and other related events as needed.

we're the driving team behind groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhsic hardware description language (vhdl)), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a hardware board design engineer, you will own the electrical design of complex high performance computing (hpc) systems. you will drive the development of next-generation ai accelerator boards, ensuring they meet signal integrity, power delivery, and thermal requirements. you will work cross-functionally with silicon (asic), signal integrity, power, mechanical, and manufacturing teams to bring products from concept to mass production.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud.  cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the schematic capture and component selection for high-density, multi-layer printed circuit boards (20+ layers) incorporating high-power asics (tpus/cpus), fpgas, and high-speed memory (high bandwidth memory/ddr5).
design and validate high-speed interfaces including peripheral component interconnect express (pcie) gen 6.0/7.0, 400g/800g/1.6t ethernet (pam4). collaborate with signal integrity (si) engineers to define routing constraints and stack-up.
design multi-phase power regulators (vrms) capable of delivering 1000a currents with fast transient response for ai processors.
work closely with pcb layout designers to guide placement and routing of critical signals and power planes.
lead the lab bring-up of first-silicon/first-board. debug complex hardware issues using oscilloscopes, time-domain reflectometers (tdrs), and logic analyzers. root-cause failures to component, assembly, or design issues

in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the schematic capture and component selection for high-density, multi-layer pcbs (20+ layers) incorporating high-power asics (tpus/cpus), fpgas, and high-speed memory (hbm/ddr5).
design and validate high-speed interfaces including pcie gen 6.0/7.0, 400g/800g/1.6t ethernet (pam4). collaborate with signal integrity (si) engineers to define routing constraints and stack-up.
design multi-phase power regulators (vrms) capable of delivering >1000a currents with fast transient response for ai processors.
work with pcb layout designers to guide placement and routing of critical signals and power planes.
lead the lab bring-up of first-silicon/first-board by debugging hardware issues using oscilloscopes, tdrs, and logic analyzers to root-cause failures to component, assembly, or design issues.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as part of our server chip design team, you will use the asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.the ml, systems, & cloud ai (msca) organization  designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the design activities at ips, subsystems(s.s) and SOC.
plan, execute, track progress, assure quality, report status of the assigned activity.
lead a team of designers both directly and in teams.
define the block/ SOC level design documents such as micro architectural specifications.
own ip, s, SOC strategies for clocks, resets, and debugs. enforce global methodologies and drive enhancements.

The Senior Professional Services Consultant is an important role as they will own the implementation of our product for our customers. We're looking for a passionate and motivated team member who will partner with our customers to design and build solutions that enhance the user experience across multiple websites and platforms. The ideal candidate is passionate about technology, solutioning, and customer success. The Sr Professional Services Consultant will report to the Director of Professional Services EMEA.
What You'll Own
Our Implementation: Design, build, and implement interactive experiences for our customers to drive business impact, such as enhancing their end-user onboarding experience and accelerating feature adoption.
Consultation: Work closely with customer application owners to understand their business objectives, pain points, and end-user needs. Provide expert advice and recommend our solutions that align with their goals and improve user experiences.
Project Management: Lead end-to-end our projects, collaborating with customers, internal stakeholders, and the development team to ensure successful delivery within scope, timeline, and budget.
Data Analysis: Monitor and analyze our usage data and user feedback to identify opportunities for optimization and improvement. Constantly strive to increase our effectiveness and user engagement.
Knowledge Transfer: Conduct training sessions for customers on our best practices, ensuring they can make the most of the product and effectively utilize its features to enhance their applications.
Troubleshooting: Identify and resolve any issues related to our implementation, ensuring smooth functionality across different platforms and devices.
Collaboration: Foster strong cross-functional collaboration with UX/UI designers, developers, customer success teams, and other stakeholders.
** Please note: The work week for this position is Monday - Friday (Sunday is a day off).

We are seeking a Digital Adoption Project Lead to join our SAP Embedded Program. This role is responsible for the end-to-end management and delivery of digital adoption initiatives embedded within SAP platforms, ensuring successful execution against agreed scope, timelines, and business outcomes.
The Project Lead acts as the primary point of ownership for assigned SAP platforms coordinating cross-functional resources, managing expectations, and driving delivery across complex SAP release cycles. This role focuses orchestrating delivery, stakeholder alignment, and program success.
So what will you actually be doing?
Project & Delivery Ownership
Own the end-to-end delivery cycle of SAP Embedded digital adoption projects, from intake through launch and post-go-live maintenance, including timelines, milestones, and ensuring high-quality delivery
Ensure delivery aligns with pre-agreed scope, success criteria, and program objectives.
Plan and coordinate resource allocation across our R&D, Solutions Engineers, Designers and supporting teams.
Drive regular project governance cadences, including status updates, risk reviews, and stakeholder check-ins.
Stakeholder Management
Serve as the primary point of contact for assigned internal customers, building and maintaining strong, trusted relationships with all stakeholders.
Act as an advocate for technical and operational needs within the SAP Embedded Program.
SAP Release & Environment Coordination
Maintain a deep understanding of SAP release cycles, system changes, and deployment timelines.
Coordinate adoption activities in alignment with SAP releases, upgrades, and process changes.
Ensure dependencies between SAP changes and digital adoption deliverables are clearly identified and managed.