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We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

We are widely considered to be one of the technology worlds most desirable employers, we own the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services.


The Chip Design group within our Networking Business division is looking for an experienced Program Manager to join its team.
The Program Manager will oversee the planning, execution and end-to-end tracking of Chip Design activities across various professional functions and organizations. The Program Manager will drive planning processes and governance execution of the Chip Design projects. He/She will work with executives and engineers within the organization and with all the interfacing organizations, while aligning with corporates Roadmap, priorities and targets.

What will you be doing:

Collaborate with project managers and engineering groups to align with the company's strategy, targets and tools.

Coordinate between all project stakeholders through all projects life cycle both Pre and Post Silicon, within Chip Design organization, and external groups like Corporate groups, BE, Architecture, Software, Firmware, Operations, etc.

Promote the use of managerial, data-driven decision-making, identify and emphasize potential issues and risks in project implementation.

Develop and implement Chip Design methodologies and Project management processes and tools.

The team leads the development of networking infrastructure for our next-generation data centers, focusing on accelerated performance while enabling optimized end-to-end GPU connectivity, focusing on datacenter-level optimized solutions for AI. As a leader of our Hardware Engineering team, you'll guide, encourage, and drive a team of highly skilled hardware engineers, providing them with stimulating and ambitious assignments and enabling them to stay creative and motivated while delivering products on schedule.

What You'll Be Doing:

Build the best team to design and execute high-performance optical transceivers.

Be a key member of the technical leadership team developing world-class optical interconnects.

Lead innovative high-performance optical module design from concept to mass production.

Collaborate with and integrate all HW project disciplines: Board Design, Assembly Process, Mechanics, Thermal, PCB Layout, Production Engineering, Software/Firmware, Procurement, NPI, and more.

Plan and oversee your teams work on multiple simultaneous development projects in coordination with the broader leadership team. Manage direct reports, set goals, provide coaching, conduct performance appraisals, plan careers, and make compensation recommendations.

Collect, examine, and filter requirements from internal customers such as marketing, software, and systems engineering to assemble a comprehensive plan of record for next-generation switches while planning resource allocation for projects and assign team members effectively.

Schedule projects, create realistic outcome estimates, and drive timely, successful execution for high-volume manufacturing.

This position is hands-on and will require a deep understanding of all technical/engineering aspects of the project with intimate familiarity with the entire development flow. From a technical standpoint, you will lead and support engineering teams in the following areas: specification definition, electrical schematics, component selection, layout guidance, hands-on lab testing, production processes, qualification workflows, micro-architecture development, verification, characterization, design for testability, cost optimization, reliability, and more.

Our HW team in Israel is looking for a senior Electrical validation manager to join the HW System qualification Group. The team leads the qualification of networking infrastructure for our next-generation data centers focusing on accelerated performance while enabling optimized end to end GPU connectivity.

Our Networking division provides innovative InfiniBand and Ethernet solutions for various industries.

What you'll be doing:
Lead the Networking organization Electrical validation activities.
Build custom Hardware electrical validation test plans for devices and component level qualifications.
Manage multiple electrical validation activities. Coach, develop, and mentor team managers. Conduct employee performance evaluations. Support other managerial tasks of team as needed.
Lead your team in applying electrical validation/test principles to build test plans and develop tools for validation.
Collaborate and integrate with all HW team: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, and more.
Support validation and approval of alternate/second source components for the devices. Build validation plan and then perform validation to qualify it.

We are seeking a highly skilled and expert Verification Lead to join our PCIe Firmware team. In this role, you will be responsible for supervising the verification plans, monitoring their execution within the teams, guiding engineers through the verification implementation, and tracking coverage, Coverity, and other relevant statistics. You will be joining a team dedicated to developing groundbreaking technology and building the core technology of next-generation our devices across various fields, including low-level C layer between hardware and firmware, C++ verification environment, automation challenges, and Python testing environment.

What youll be doing:

Develop and lead verification plans, ensuring they are driven effectively within the teams.

Provide guidance to engineers on verification implementation within the verification environment.

Monitor coverage, Coverity, and other statistics to ensure comprehensive verification and optimization of next-generation our products.

Work closely with firmware design, chip design, software, and architecture teams to define and craft both legacy and new low-level firmware flows.

Enhance methodologies and automated processes to improve efficiency and effectiveness.

Our Analog Layout design team is looking for a Senior Analog Layout Design Engineer someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs. We have continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our lifes work, to amplify human creativity and intelligence.

What you'll be doing:

Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools.

You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.

Job duties will include floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis.

We are expanding our System Integration & Validation group and invite you to explore Space with us and join our group of experts.
Job Description:
Define Integrations and integration testing requirements based on product requirements and technical system specifications.
Define the system integration approach and system integration tests for multidisciplinary projects and applications.
Develop and Design test cases and tools for integration and validation.
Plan, implement and conduct system tests based on test plans.
Debug of hardware and software embedded systems.
Create detailed integration & test reports.
Hands-on in various lab set-ups (analog, digital, software, Firmware).

​If you are looking to make an impact, come and join a team developing the next generation of space communication technology.
Our mission is to revolutionize the way satellites, space robots and spacecrafts communicate through deep space, in earth orbit and with ground stations. Our technology is based on space proven state-of-the-art proprietary architecture that enables a different approach to the way space communication systems are designed.
We are looking for experienced FPGA Engineers to lead innovation in the next generation space connectivity technology.
What you will be doing​:
Design and manufacture systems including ICs by RS and SoC type FPGAs
Design and implement high-speed digital signal processing algorithms.
Design for highly robust, distributed systems with emphasis on managing physical effects that originate from the harsh space environment.
Implement DSP algorithm on SoC type FPGAs.
Key contributor to Digital, Modem architecture and design.
Lead technical reviews with key stakeholders.
Work closely within a multi-disciplinary team to lead high-impact technical decisions about system design, implementation, and verification.