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Will you help us design future generations of revolutionary products? Are you an engineer with a strong foundation and real passion for building new technologies? Do you have track record leading DFT efforts for complex chip designs? Imagine what you could do here. new ideas have a way of becoming excellent products, services, and customer experiences very quickly. Every single day, people do amazing things . Do you want to impact billions of users by developing extraordinary products with a prime focus on accuracy and performance of the product? You will become part of a hands-on development team that furthers engineering excellence, creativity and innovation.
Dynamic, inspiring people and innovative technologies are the norm here. We want you to join our team if you are an innovative engineer with the dream to research and develop solutions that do not yet exist. In this highly visible role, you will be at the centre of a System-on-Chip design effort. collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
Description
Lead the complete DFT solutions in a chip design by working with chip DFT team to document DFT specifications, and define the SoC test interface Develop and implement DFT architecture Work with the validation team to verify DFT implementations and implement design changes Generate structural test vectors, analyze and improve coverage Work with designers on STA, physical, power and logical issues Work with Test Engineers to bring up test vectors on silicon.

we relentlessly strive to create products that enrich peoples lives. Are you passionate about solving unresolved challenges and revolutionizing the industry? We have an exceptional opportunity for an exceptionally talented IP timing lead to join our dynamic group. As a key member of this team, you will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers daily. This role is for an IP timing Engineer who will empower us to produce fully functional first silicon IP designs. Your responsibilities will encompass all phases of pre-silicon development, from defining the constraints to achieving high-quality tape-out..
Description
In this role, you will be responsible for developing and owning IP level Netlist generation (Synthesis, UPF , scan insertion, external IPs integration) & timing constraints, for both regular and custom requirements, from synthesis to sign-off, ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure, with the CAD team to understand and develop the flow, and with the Physical Design team to finalize and sign-off the timing. Additionally, you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.

we are a leader in disaggregated high-scale networking solutions for service providers and AI infrastructures. Founded in December 2015, our company created a radical new way to build networks by adapting the architectural model of the cloud to telco-grade networking. This solution accelerates network deployment, improves the networks economic model, and radically simplifies network operations. With customers including Comcast, Orange, and KDDI - over 80% of AT&Ts network traffic now runs through a disaggregated core powered by our company's software. our company's Network Cloud-AI solution, based on the same technology, was introduced to the market in 2023, providing the highest-performance Ethernet-based AI networking solution, and is already deployed by Hyperscalers, NeoClouds and Enterprises. Raising over $587 million in three funding rounds, our company continues to deploy the most innovative network infrastructure and is looking for the most talented people to be part of this journey.
The Role
We are seeking a highly skilled and experienced multidisciplinary engineer with a strong background in system design to join our team. In this role, you will contribute to our upcoming projects and play a key part in the rapid expansion of the Ethernet networking market.
As a such, you will be responsible for developing high-speed digital and analog circuit boards used in Ethernet products. Your duties will include designing board schematics, overseeing PCB layout, and conducting lab debugging. Additionally, you will be responsible for evaluating new hardware solutions, providing technical leadership in troubleshooting and reviewing schematics, layouts, and design for manufacturability (DFM), as well as managing components selection.

we are a software company revolutionizing the networking space with a cutting-edge routing stack that runs on dedicated whitebox hardware. Our platform disaggregates hardware from software, giving service providers the scale and flexibility to operate their networks more efficiently. We collaborate closely with external ODMs to bring our solution to life on best-in-class hardware. HW platforms, built by the ODM, are high-end networking devices (mainly routers ) with high-speed network processors, CPU, BMC, and other peripherals.
Position Overview
We are seeking a Hardware Program Manager to lead and manage all hardware-related activities across the product lifecycle. This includes managing the interaction between internal R&D teams and external hardware vendors ODMs, ensuring that hardware development aligns with our company's software stack requirements and product timelines. This role bridges the technical and organizational aspects of hardware developmentfrom defining hardware requirements, planning integration with software, managing release schedules, to resolving customer-facing issues. The ideal candidate will bring a blend of deep technical expertise in hardware systems and exceptional soft skills to coordinate cross-functional teams across legal, product, architecture, R&D, supply chain, and vendor partners.
Key Responsibilities
End-to-End HW Program Ownership: Lead and manage hardware development activities from initial requirements
through production, validation, and deployment.
Cross-Functional Coordination: Collaborate with product management, systems architecture, software R&D, legal, and
supply chain teams to align on requirements and execution plans.
External Vendor Management: Serve as the main technical point of contact with ODMs, managing technical discussions,
tracking progress, and resolving issues.
Planning & Execution: Drive hardware and firmware planning, including schedule alignment with software integration
cycles and overall product release plans.
Bug & Issue Management: Lead bug triage and resolution processes for hardware and firmware, including customerreported issues.
Release Management: Coordinate and manage content and timelines for hardware and firmware releases, ensuring
quality and timely delivery.
Risk Management: Identify and mitigate technical and schedule risks throughout the project lifecycle.
Technical Leadership: Provide technical guidance and hands-on engagement in board-level design issues, validation
planning, hardware bring-up, and debugging.
Stakeholder Communication: Provide regular status updates to executive stakeholders and drive decisions at critical
project milestones.

Join the Silicon One PHY System Team, a key part of silicon development. You'll be at the forefront of defining, implementing, and validating advanced PHY and system solutions for next-generation network devices.

Your responsibilities will include:
Defining features for future devices utilizing cutting-edge silicon technologies.
Developing and optimizing PHY firmware and calibration processes.
Driving system-level definitions, operations, and post-silicon validation.
Collaborating with cross-functional teams to ensure high-quality deliverables.

As a Signal/Power Integrity Engineer, you will play a key role in ensuring the performance and reliability of our high-speed SerDes IP, covering silicon, package, and board-level analysis. You will collaborate across multiple fields, including analog design, silicon integration, PCB & package design, and mechanical engineering.

Provide implementation guidelines and feedback to silicon, package, board, and system design teams.
Design and simulate high-speed SerDes signals and perform co-simulation of package and PCB in HFSS.
Conduct feasibility studies, design verification, and sign-off processes, including lab correlation.
Perform Power Distribution Network (PDN) analyses, including model generation and time-domain simulation.
Work closely with backend, package, and board design teams for bump-out and ball-out optimization.
Drive chip-package-PCB co-design of SerDes at 112Gbps and beyond, ensuring signal and power integrity best practices.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.

As part of our team, youll contribute to the development of our next-generation network devicesSilicon One. Our team operates in a startup-like environment within a stable and leading corporation.

As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.

What You'll Do:
You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

We are excited to announce that the Silicon One team is undergoing rapid growth, and we have opened multiple positions for Junior C++ Software Engineers!

You'll be joining Silicon One Israeli team which is the core center of our SW and ASIC design. You'll be part of the group driving our groundbreaking next-generation network devices - Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs.

You'll develop Core Software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.

In this role, you will:

Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed.

Location: Caesarea, Israel.

Commissioning Manager Looking to combine your technical expertise with hands-on field work in the renewable energy sector?

We are looking for an outstanding System Qualification Engineer capable of understanding complex systems, to participate in the Qualification process for its revolutionary products.
Responsibilities:
Coordinate and execute hands-on functional and reliability-related test activities on full systems and components
Select, calibrate, and install the right instrumentation (such as strain gages, thermocouples, and accelerometers)
Collect and analyze data utilizing data acquisition and software processing tools like Python scripts
Based on collected data and information, determine if specifications, regulations, customers expectations, and acceptance criteria are satisfied According to automotive standards
Generate formal technical reports, and present conclusions to stakeholders
Conduct Failure Analysis investigations, diagnose failed components and find the root cause for the failure
*Employment through 3rd party.

We are developing state-of-the-art LiDAR sensors and advanced perception software for the automotive industry. We are looking for a Senior System Engineer to join our fast-paced, innovative team developing LiDAR systems for autonomous vehicles. We are looking for a talented hands-on individual contributor and feature owner, to lead multi-disciplinary systems development and integration, from KPI and data analysis and algorithm prototyping to customer delivery.
Responsibilities
Lead system engineering activities across the LiDAR development lifecycle, from concept through validation and integration into vehicle platforms.
System-level testing, characterization and modeling.
Develop FW algorithms, calibration methods and post processing solutions to complex challenges.
Integrate multi-disciplinary sub-systems, including electro-optics, electronics, firmware, mechanics, software, etc.
Contribute to requirements definition, system design, and design reviews with cross-functional teams.
Develop Python/MATLAB-based simulations, prototypes, and automation tools for rapid proof-of-concept and laboratory equipment control.
Communicate technical results and lead development processes according to Automotive SPICE standards.