לוח משרות דרושים חשמל ואלקטרוניקה בירושלים וסביבתה

Join our advanced packaging team to define and develop cutting-edge semiconductor package solutions for automotive-grade digital and RF System-on-Chip (SoC) products. Youll collaborate with internal teams and external OSATs to deliver high-performance, manufacturable, and reliable packages that meet stringent automotive standards.
What will your job look like:
Define and specify advanced package architectures for digital SoCs and RF ICs in automotive applications.
Perform substrate design for flip-chip BGA (FC-BGA) packages, including stack-up, routing, and ball-out optimizations.
Evaluate and select substrate technologies, materials, and package solutions based on performance, cost, and reliability.
Collaborate with OSATs to define and validate assembly materials and process flows.
Work closely with internal teams such as Backend, SIPI, Product Engineering, and Quality & Reliability to ensure seamless integration.
Monitor yield, quality, and manufacturability across package development and production stages.
Support DFM reviews and ensure compliance with automotive standards and customer requirements.

The EyeQ SoC Performance Modeling and Profiling team is part of the EyeQ Platform Group (EPG), working on both current and next-generation designs for ADAS (Advanced Driver-Assistance Systems) and Autonomous Vehicles (AV). Performance models and profiling tools are essential components of the EPG infrastructure they are used during the hardware architecture definition phase of the EyeQ chip and by software developers to optimize performance.
What will your job look like:
You will be part of team that develops EyeQ SoC Performance Modeling environment and emulators
You will work on SOC performance analysis and optimizations.
You will be running HW benchmarks, to measure HW performance and to calibrate the simulation environment to match the performance of the silicon board.
You will be working on HW performance analysis and tuning, and influence future company EyeQ SoC design.
You will have the opportunity to work on open-source simulation and profiling tools and adopt them to our company's needs.
You will work closely with HW architects and SW/Algorithms developers.

As the Silicon Engineering Manager you will be responsible for improving silicon-photonics yield and performance through data-driven analysis, cross-functional collaboration and proactive issue resolution.

You will serve as the key interface between R&D, Process and Production teams, ensuring efficient data flow, rapid issue identification and continuous process improvement across wafer fabrication, device testing, and packaging stages.

Responsibilities:
Perform silicon process and chip-level data analysis, establishing correlation between chip and wafer performance.
Lead process debug and yield loss analysis at chip/wafer level, driving root cause investigations and corrective actions.
Manage engineering approval forum to release production material.
Collaborate closely with vendors to implement new product tests and resolve technical/process issues.
Act as a key interface between design, testing, and production teams, ensuring alignment across the product lifecycle
Oversee and coordinate the transfer of data related to silicon design, testing, fabrication, and characterization between Production and R&D departments.
Develop and implement data management strategies to ensure data accuracy, security, and accessibility.
Maintain proper documentation of data transfer protocols, version control, and data integrity checks.
Support data analysis efforts to improve silicon performance, yield, and quality.
Ensure compliance with company policies and industry standards related to data security and confidentiality.

We are looking for a Photonics Layout Engineer to join our integrated photonics design team - This position is also well-suited for Analog Layout Engineers who are interested in transitioning into photonic integrated circuit (PIC) design.

In this role, you will be responsible for creating, optimizing and validating PIC layouts, ensuring manufacturability, performance and compliance with foundry design rules. You will work closely with device designers, process engineers, and tape-out teams to deliver high-quality layouts of silicon photonics PICs.

Strong candidates will have hands-on experience with industry-standard layout tools, especially Cadence Virtuoso or similar software.

Understanding of photonic components, waveguide routing and automated layout generation is a major advantage.

You will also contribute to layout methodologies, PCells, and design automation flows to accelerate PIC development.

Responsibilities:

Develop and implement mask layouts for photonic integrated circuits using Cadence Virtuoso or similar software.

Create and maintain PCells for photonic building blocks (waveguides, couplers, modulators, gratings, etc.).

Perform waveguide routing, ensuring correct connectivity, bend radius limits, and low-loss optical paths.

Verify layouts using DRC, and LVS to ensure compliance with foundry requirements.

Collaborate with device designers to translate basic schematics and specifications into Software schematics and manufacturable layouts.

Optimize layouts for performance, yield, and compactness while adhering to technology constraints.

Participate in photonic design automation tool development and workflow improvements.

Prepare and manage data for tape-out and support mask review processes.

Debug layout and rule-check issues and propose corrective actions.

We are seeking a talented and motivated R&D Physicist to join our company.

In this role, you will be responsible for designing and carrying out experiments for SiPh chip performance and characterization, performing and analyzing laboratory experiments of chip level optical systems assembly, and developing and managing setups for photonics and laser devices characterization. In this roll you will be required to travel abroad for demonstrations and exhibitions as needed.

Responsibilities:
Design and carry out experiments for SiPh chip performance and characterization.
Perform and analyze laboratory experiments of chip level optical systems assembly.
Develop and manage setups for photonics and laser devices characterization.
Provide technical support to the R&D team for experiments and data analysis.
Contribute to the development of new testing methodologies and techniques.
Ensure adherence to experimental protocols and safety procedures.
Maintain laboratory equipment and supplies.