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We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.

Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.

founded by the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging things previously disconnected from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food, and pharmaceutical companies to change the way we make, distribute, sell, use, and recycle products.

Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm, and PepsiCo.

Were seeking a highly skilled and motivated Senior Research Engineer with deep expertise in digital communication systems to join our world-class team. If you have a strong academic background, at least 5 years of relevant industry experience, and a passion for shaping the future of IoT communication technologies and standards, we want to hear from you!

Responsibilities
Drive the research and development of advanced communication technologies for ultra-low power IoT devices.
Design and evaluate algorithms for digital and wireless communication, including modulation, coding, and channel estimation.
Draft and present technical contributions in standardization bodies like IEEE, 3GPP and Bluetooth - that help shape the future of global communication standards.
Collaborate closely with cross-functional teams including systems, hardware, software, analog, and product.
Analyze technical challenges and provide innovative solutions in constrained RF and communication environments.
Stay up to date with emerging technologies and propose new research directions.

founded by the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products.
Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo.

Responsibilities
RF system performance prediction and assessment
RF system qualification and validation
Conduct tests as per test plan and analyze test data
Performing technical investigations
Problem assessments and proposal of design solutions
Prepare engineering reports including preliminary observations, data from initial tests, data analysis including any applicable screenshots or data output from test equipment, discussions of proposed solutions, test results of abatement efforts, comparisons of the baseline data with post abatement data and additional recommendations
Prepare engineering test plans, outline test methods, including required test equipment, and anticipated sequence of testing

the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products.
Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo.

looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.

Responsibilities
Lead the full verification lifecycle and methodologies. Plan, Design and Execute verification of SV/UVM Block level and Full chip environments , creating and execution test plans, tracking progress, and ensuring verification closure across diverse Mix-signals SoC simulation using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

We are looking for a Lab Engineer, Hardware & Logistics.
Your Impact:
Assemble, configure, and dismantle lab setups consisting of communication hardware from simple boards to complex systems.
Collaborate with vendors and suppliers to ensure timely delivery, setup, and maintenance of lab equipment.
Plan and support lab requirements for new projects including estimating board quantities, selecting appropriate gear, and designing connectivity schemes.
Prepare and maintain work environments for engineering teams, ensuring operational readiness.
Oversee lab logistics work with procurement and manage equipment inventory and stock planning.
Coordinate installations, upgrades, and troubleshooting across the lab infrastructure.
Work cross-functionally with engineers and operations teams to ensure the lab supports evolving project needs.

We are excited to announce that the team is undergoing rapid growth, and we have opened multiple positions for Junior C++ Software Engineers!
Location: Caesarea, Israel
Your Impact:
You'll develop Core Software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.
In this role, you will:
Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed

We are looking for a Physical Design Team Leader.
What You'll Do
You'll be joining our Physical Design team, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

We are looking for a Senior DFT Engineer.
As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.

We are looking for a Senior CAD Physical Design Engineer.
WHAT YOU'LL DO:
You'll be joining our Physical Design team , which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

We are looking for a ASIC Modeling Architect Engineer.
What You'll Do:
You'll join our architecture team, central to silicon development.
You will define features of future devices using the latest silicon technologies, focusing on Logic Design and coding.
You will be responsible for defining the device specification.

We are looking for a IC Package Design Engineer.
What You Will Do:
As a member of the Package Design Team, you will:
Lead package design tasks, being responsible for planning, coordinating with partners, and driving schedules from start to finish.
Optimize package pinouts, stack-ups, placements, power distribution, and high-speed routing while balancing functional needs, manufacturing constraints, and performance considerations.
Collaborate with silicon floor plan, signal integrity (SI), and power integrity (PI) teams to ensure design quality and efficiency.
Work closely with layout editors to implement the package design, ensuring alignment with high-speed signal and functional interface requirements.
Enhance design methodologies and procedures, collaborating with vendors and developers to improve product quality and design efficiency.

We are looking for a PHY Validation Engineer.
What You'll Do:
Youll be joining the post silicon validation team in PHY system group Silicon One group as part of the silicon development .
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

Join the team in developing a unified silicon architecture for web-scale and service provider networks.
the team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, café, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
Your Impact:
Define devices and deliver specifications to other development teams.
Work with internal and external customers to understand and define current and future requirements.
Innovate at all levels to deliver market-first features and solutions.
Conduct in-depth research to shape the architecture of next-generation networking devices.
Contribute to full-chip integration and cross-functional collaborations to enhance design methodology.
Participate in the definition and analysis of networking system solutions, ensuring they meet market and technical needs.

We are looking for a Signal Integrity Engineer .
As a Signal/Power Integrity Engineer, you will play a key role in ensuring the performance and reliability of our high-speed SerDes IP, covering silicon, package, and board-level analysis. You will collaborate across multiple fields, including analog design, silicon integration, PCB & package design, and mechanical engineering.
Provide implementation guidelines and feedback to silicon, package, board, and system design teams.
Design and simulate high-speed SerDes signals and perform co-simulation of package and PCB in HFSS.
Conduct feasibility studies, design verification, and sign-off processes, including lab correlation.
Perform Power Distribution Network (PDN) analyses, including model generation and time-domain simulation.
Work closely with backend, package, and board design teams for bump-out and ball-out optimization.
Drive chip-package-PCB co-design of SerDes at 112Gbps and beyond, ensuring signal and power integrity best practices.