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We have continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. we are a learning machine that constantly evolves by adapting to new opportunities that are hard to seek, that only we can pursue, and that matter to the world. This is our lifes work, to amplify human creativity and intelligence. Make the choice to join us today.

What youll be doing:

Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value-conscious PCBs for all business units in our company (GPU Desktop, Notebook, Automotive, Professional, Data Center, Deep Learning, and AI), all using Cadence PCB design tools.

Focus will be on the complete development of CAD layout from symbol creation, floor planning, and detailed component placement, constraints management, with a concept of topology and signal/trace integrity.

You will be responsible for the design releases required generation of artwork files, ODB++, and electronic PCB documentation.

Your designs will need to follow SI constraints, EMI/RFI control and FCC, UL and European regulations, IPC specifications and NRC regulations.

We are looking for an experienced, visionary Product Manager to lead the end-to-end product lifecycle of our advanced, multi-disciplinary Counter-Unmanned Aerial (C-UAS) platform. In this role, you will lead a highly complex multi-layer system integrating sensor technologies, including our Cyber and additional layers such as: Radar, Electro-Optics (EO/IR), Jammers, etc.
Key Responsibilities:
Inbound Product Management & R&D Collaboration: Work closely with R&D teams. Collaborate with the PLUS R&D lead, System engineers, SW and HW teams about all product SW & HW, including the product's current development and roadmap aspects.
Cross-Functional Leadership: Lead and synchronize activities across R&D, System Engineering, Operations, and Sales to ensure aligned execution.
Support Pre-Sale and Sales teams with deep technical expertise, high-level customer presentations, competitive analysis, and Go-To-Market (GTM) strategies.
Partner relationship: Drive strategic collaboration and technical integration with local and international subcontractors and technology partners.
Product Innovation: Bring out-of-the-box thinking to drive product maturity, identify unique value propositions, and maintain a competitive edge in the global market.

We are seeking a highly skilled Senior Communication PHY Algorithms Engineer.
This senior role is focused on the end-to-end research, design, and implementation of digital receivers for proprietary drone communication signals.
Responsibilities:
Mathematically characterize complex communication and signal detection problems. Analyze and assess design trade-offs based on both performance metrics and implementation complexity.
Develop and maintain simulations using MATLAB and Python.
Design digital receiver modules to be implemented either by FPGA of SW.
Implement features directly in SW or technically lead and verify the FPGA implementation efforts of the FPGA engineer.
Accompany the integration process of the feature until its end-to-end operation.

We are looking for an experienced Senior Signal Integrity Engineer to join our Hardware Engineering team. This role focuses on ensuring optimal signal integrity for high-speed interfaces, including Ethernet, PCIe, DDR5, and other next-generation technologies. As part of the team, you will be responsible for performing signal integrity analysis, developing signal integrity models, and ensuring electrical compliance for high-speed SERDES I/Os.
Responsibilities:
Conduct signal integrity analysis and simulations for high-speed interfaces such as 112Gbps Ethernet, PCIe Gen5, and DDR5 interfaces.
Develop and implement signal integrity guidelines for PCB design, ensuring high-performance and low-loss signal paths.
Analyze and resolve signal integrity issues related to high-speed interfaces, including reflection, crosstalk, and power delivery network (PDN) issues.
Collaborate with PCB layout engineers to optimize design for signal integrity, ensuring compliance with electrical standards and high-speed design best practices.
Perform time-domain and frequency-domain analysis, including loss, jitter, and eye-diagram analysis.
Utilize EDA tools such as Ansys SIWAVE, HFSS, or similar for simulation and validation of signal integrity designs.
Work closely with cross-functional teams to integrate signal integrity considerations into the overall hardware design process.
Develop behavioural models based on measured signal integrity data to inform future design and simulation work.
Conduct pre- and post-layout simulations and measurements for high-speed signal interfaces.