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we are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you will be doing:
Join Beer-Sheva group, working on RiscV processors platform.
Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work will involve design and might involve any or all aspects of chip development including micro-architecture, dv
Work closely with firmware and other groups around the globe.

As a Technical Support you will:
Handle customer requests professionally, maintaining SLAs and high satisfaction rates.
Own complex cases and escalate effectively across internal teams (R&D, Product, SecOps, etc.).
Troubleshoot technical issues, conduct root cause analysis (RCA), and deliver resolutions.
Collaborate cross-functionally with Engineering, DevOps, SecOps, FinOps, SMB, SE, Product, FieldOps, Finance, CompOps, Network, and Risk.
Communicate clearly and empathetically with customers via HubSpot, phone, and email.
Verify functionality in Sandbox and Production environments to support accurate issue resolution.
Document solutions, best practices, and contribute to the internal knowledge base.
Support and guide Tier 1 agents, acting as their escalation point.
Assist with the onboarding and training of new Tier 1 agents.

We are seeking a highly motivated Chip Design Architect to join our team of experts and help shape the future of high-performance computing. Our next-generation Infiniband and NVL switches will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used in industries such as finance and research labs. As a Chip Design Architect at our company, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation of switches that will be used by top researchers and engineers around the world. The products you'll develop will be integrated in many leading-edge compute clusters, and supercomputers, and you'll be part of a team with a strong track record of success.
What you will be doing:
Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and hardware teams, to ensure the successful execution of the project.
Define the HW boot, clock and Reset architecture for Switch ASIC
Develop slow-speed interface architecture specifications and design guidelines, conduct trade-off analysis for different architecture options, and oversee the implementation of the chosen architecture by the chip design / FW / SW teams.

With the growing demand for traffic bandwidth in datacenters, efficient physical high-speed communication becomes a crucial part of the development of silicon ASCs that serve networking infrastructures. We are looking for a PHY (Physical Layer) Architect for our Architecture team. We are positioning you to a key role to face this challenge and become part of our team, so we can continue developing the best devices in the industry.
our company's networking architecture group is seeking for a highly skilled, leading engineer to explore, and define the Physical layer of our products. As a lead engineer, you'll be responsible to define and drive features and have responsibility on the Physical layer architecture. The role will include definition of both the hardware features and the firmware/software that is involved in operating the physical layer communication, with emphasis on the former. We are searching for hardworking, enthusiastic, engineer which has both highly technical skills as well as good personal skills, in order to be able to lead cross groups activities.
What you will be doing:
Lead projects across team, starting from processing requirements and definitions from customers and translating those into detailed technical specification for firmware architecture, system embedded software, user interface and high-level design.
Supervise the implementation of projects by team-leaders / developers / QA, participate in low level design reviews, QA test plans reviews, and keep track of changes and handle obstacles.
Define the architecture of implementing physical layer standards into our company's ASIC devices.
Involved in standard bodies activities and definition of next generation protocols.
Define features for the phy layer, to exploit interoperability between different generations of communication.
Be involved in product definition and the high-speed protocols that the our company networking devices will support.
Work closely with multi-functional teams - design, backend, system, marketing, firmware, driver, etc. Provide architecture definitions and as a result converge on key design decisions.
Become focal point for our ccompanys physical layer networking communication devices.

We are seeking a highly skilled and experienced Senior Risk Operations Analyst to join the RiskOps Infrastructure & Modernization team. In this pivotal role, you will be responsible for driving the modernization, enhancement, and automation of our risk & compliance processes and workflows across the organization. You will play a critical part in strengthening our risk and compliance operational frameworks, ensuring operational efficiency, adhering to regulatory requirements and fostering a culture of continuous improvement within a rapidly evolving global fintech environment.

Responsibilities:
Lead the strategic design and implementation of enhanced and automated and AI-based risk operations and compliance operations processes and workflows, leveraging cutting-edge technologies and best practices.
Drive the improvement and creation of comprehensive RiskOps knowledge bases, procedures, training programs, and policies to ensure consistency, efficiency, effectiveness and clarity across all relevant teams.
Monitor progress and measure performance, embrace ongoing improvements framework.
Provide support during audits and regulatory examinations.
Support cross-company processes and ad-hock tasks.
Continuously monitor the performance, progress, and exposure of risk-related activities, ensuring the effective implementation of recommendations and remediation plans.
Identify, assess, and address potential operational and technological risks within the risk/compliance/operations infrastructure, collaborating with relevant departments to establish robust mitigation strategies.
A data-driven approach, utilizing insights to inform decisions and drive continuous improvement.
Promote a culture of proactivity, efficiency, innovation and continuous learning within the risk and compliance functions.

The employee in this role will develop technological solutions for the Finance department, including backend work in Python and frontend work in React. The position involves collaborating with finance team members and accountants to deliver efficient solutions for the departments needs. The developer will be responsible for managing projects from definition to launch, with support and guidance as needed.

Key Responsibilities:
Develop software systems to improve processes in the Finance Department, using Python and React.
Collaborate with finance staff and accountants to understand business needs and adapt solutions accordingly.
Provide quick and effective solutions to technological problems, while maintaining code quality and system reliability.
Take part in the full development lifecycle, including planning, development, integration, and maintenance.
Meet deadlines and execute plans according to the departments changing needs.
Work independently and proactively, taking responsibility for assigned tasks.
Communicate progress and updates to relevant stakeholders.

we are looking for best-in-class Physical Design Team lead to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Leading and mentoring Physical Design-Backend team.
Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.
Take part in project definition towards POR, close interaction with other domains such as FE, ARCH.

we are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you will be doing:
Join Beer-Sheva/Tel-Aviv group, working on verification/design in the field of encryption accelerators.
Verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work will involve verification and might involve any or all aspects of chip development including design and micro-architecture.
Work closely with firmware and other groups around the globe.
Work mode: Hybrid home-office.

As a Software Developer you will be responsible to:

Play a key role in designing and implementing infrastructure solutions to support our development and deployment processes. This role requires a versatile individual with strong technical skills, an out-of-the-box thinker, and a passion for solving challenging problems in cloud-based environments.

Key Responsibilities:
Develop, maintain, and optimize Python-based services and tools for cloud platforms (AWS preferred).
Design and implement scalable and secure infrastructure solutions, leveraging modern cloud technologies.
Build and maintain APIs, microservices, and server-side applications using Python frameworks.
Collaborate with cross-functional teams to integrate CI/CD pipelines and improve deployment efficiency.
Troubleshoot and resolve technical bottlenecks in cloud-based systems.
Contribute to system architecture design and ensure best practices are followed.
Stay up-to-date with emerging technologies and trends to continuously improve development and deployment processes.

We are now looking for a Senior Chip Design Verification Engineer to join our Switch Silicon team.As a Chip Design Engineer at our company's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What You'll Be Doing:
Work in a design/verification team which develops core units within the Switch silicon.
Micro-architecture of dynamic verification environments planning for units and modules.
Design dynamic verification environments of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

We are now looking for a best-in-class Senior Chip Design Engineer to join our outstanding GPU-Networking Silicon Engineering team. As a DV Engineer at our company's GPU-Networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry our companys GPU Super-Chip.
What youll be doing:
Work in a DV (Design Verification) team that has a global responsibility over deliverable units and clusters to the silicon GPU
Integrations and Full-Chip models
Verification of chip blocks/entities according to specifications under challenging constraints
Your daily work will involve all aspects of Design Verification : Planning, Coding, Coverage and Integration.

As a Senior Full Stack Developer you will be responsible for:
Full Stack development using Node.js & React.
Development high scale cloud-based solutions in the Fintech area.
Development in cutting edge technologies.
Position will be involved in design and implementation of low latency, high availability and high-performance services.
Development in a very dynamic environment which provides ability to learn and implement new technologies.

We are now looking for a Senior Chip Design RTL Design Engineer for the Switch Silicon group.
As a Chip Design Engineer at our company's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What you'll be doing:
Work in a combined design and verification team which develops some of the switch silicon core units.
Plan and Design RTL units / blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.
Build reference models, verify and simulate chip blocks/entities according to specifications.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

At our company, you will be joining a team of dedicated Physical Design Engineers who excel in developing high-speed communication devices. Our team is recognized for delivering highly efficient and low-latency products. Join us to contribute to groundbreaking chips in a professional environment. This is an ambitious role where you will compete and excel in a collaborative environment.
You will be empowered to determine and successfully implement world-class solutions. Join us to be part of a team where your work will be flawless, and your career will thrive in our encouraging and inclusive culture. our company has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!
What you'll be doing:
Learn and implement the complete place & route flow, using sophisticated software tools.
Be responsible for the physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed to and work on a variety of exciting designs, including high cell count and high frequency blocks, resolving timing and congestion problems.
Engage in the complete design chip development flow (RTL2GDS) including synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

we are looking for best-in-class STA Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
STA analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part inflows development.