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לפני 1 שעות
חברה חסויה
Location: Haifa and Hod Hasharon
Job Type: Full Time
We are looking for a Senior AI Modeling Architect to define and model the architecture of our next-generation AI processors. In this role, you will serve as a key technical authority - bringing not only strong modeling capabilities, but also the architectural vision to propose and drive end-to-end solutions to complex design challenges.
You will work at high levels of abstraction, partnering closely with HW and SW architects to co-invent optimal solutions, validate them through simulation, and influence design decisions based on experimental data.
Responsibilities:
Model CPU/AI processor functionality and performance using SystemC and pre-silicon simulation environments
Define and drive architectural solutions - not only identify problems, but come with concrete proposals and alternatives
Partner with lead HW and SW architects to co-design features and evaluate trade-offs across the stack
Analyze bottlenecks and performance on workloads reflecting future AI use cases Provide proof-of-concept implementations for new architectural features and design alternatives
Potentially lead feature definition in addition to the modeling role
Requirements:
B.Sc. or higher in Electrical Engineering, Computer Science, or related discipline
10+ years of experience in VLSI/processor architecture (exceptional candidates with less experience will be considered)
Strong hands-on experience with SystemC modeling
Solid background in AI workloads and AI hardware architecture
Experience in HW/SW co-design and architectural trade-off analysis
Ability to operate at high levels of abstraction and drive architectural decisions from simulation data
Skills:
Strong independent technical judgment - able to come with a solution, not just a model
Excellent interpersonal and collaboration skills
Creative, self-driven, and a strong team player
Advantages:
Experience in CPU/DSP/GPU processor core architecture definition
Familiarity with AI accelerator design and large-scale inference solutions
Exposure to ISA definition or new instruction design.
This position is open to all candidates.
 
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לפני 20 דקות
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סוג משרה: משרה מלאה
אנחנו מגייסים מהנדס/ת פיתוח למחלקת R&D מובילה (~60 עובדים), לעבודה על פיתוח כרטיסים אלקטרוניים לספקי כוח מתקדמים.

תחומי אחריות:
פיתוח ותכנון כרטיסים אלקטרוניים לספקי כוח
עבודה על מערכות DC-DC, AC-DC ו-PFC
אינטגרציה, בדיקות וולידציה למודולים
ביצוע אנליזות ביצועים, אופטימיזציה וניסויי מעבדה
ליווי המוצר מקונספט ועד מוצר מוגמר
דרישות:
ניסיון של 4-5 שנים בפיתוח ספקי כוח / מעגלי הספק ואנלוג
ניסיון בתכנון DC-DC, AC-DC ו-PFC
ניסיון בתכנון מעגלים אנלוגיים (Feedback, מגברים, רכיבי מיתוג)
עבודה עם כלי סימולציה: Matlab / PSpice / LTspice
ניסיון עם רכיבי הספק: GaN, SiC, MOSFET, IGBT
ניסיון בעבודה עם ציוד מעבדה (Oscilloscope, Spectrum Analyzer)
ניסיון בתכנון PCB (Altium / Cadence / OrCAD)
היכרות עם פרוטוקולי תקשורת: CAN, SPI, I²C
תואר בהנדסת חשמל ואלקטרוניקה המשרה מיועדת לנשים ולגברים כאחד.
 
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לפני 1 שעות
Location: Hod Hasharon and Haifa
Job Type: Full Time
Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.
Requirements:
BSc or higher degree in Computer Science/Engineering or related discipline from a leading university. (Alternatively, exceptional proven track record in similar tasks)
3+ years of experience in one or more of following disciplines: development of simulators/emulators for CPUs, definition of CPU features, HW/SW co-design, Low level performance profiling and optimization of SW with exposure to CPU ISA
Fluent spoken and written English
Behavioral skills: Team player. Interpersonal skills needed to collaborate with colleagues towards achieving a technical goal
Advantageous qualifications:
Experience in SW/HW codesign or in definition of new instructions will be a great advantage
Familiarity with dense compute workloads and analysis (e.g., AI, HPC, financial, etc.)
Familiarity with Vector Architectures.
This position is open to all candidates.
 
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לפני 1 שעות
חברה חסויה
Location: Hod Hasharon and Haifa
Job Type: Full Time
Required Senior CPU Core Architect
Job Description
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.
Requirements:
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
At least 20 years of experience in one of the leading CPU companies
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
QUALIFICATIONS
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.
This position is open to all candidates.
 
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לפני 2 שעות
חברה חסויה
Location: Hod Hasharon
Job Type: Full Time
Required HW Architect team leader
About the Group
We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
our Impact:
As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing:
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence.
Requirements:
BSc / MSc / PhD in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in VLSI / ASIC design, chip architecture, or micro-architecture of complex blocks.
Proven experience leading or managing a small team of designers, verification engineers, or HW architects.
Ability to take an idea into implementation.
Strong background in high-speed networking systems, such as:
o Ethernet Switches
o NPUs
o NICs
o Traffic Managers
o Fabric Switches
o High-performance processors
Skills:
What Were Looking For
Strong technical leadership with the ability to drive architectural vision.
Excellent written and verbal communication skills in English.
Outstanding collaboration and teamwork skills across disciplines and organizational levels.
Independent, self-driven, and comfortable taking full ownership of complex challenges.
Passion for innovation and cutting-edge networking technologies.
Highly motivated with a proactive, can-do mindset.
This position is open to all candidates.
 
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לפני 1 שעות
חברה חסויה
Location: Hod Hasharon
Job Type: Full Time
Required Senior HW architect
About the group:
We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.
Requirements:
:BSc / MSc / PhD in Electrical Engineering, Computer Engineering, or a related field.
7+ years of experience in VLSI / ASIC design, chip architecture, or micro-architecture of complex blocks.
Strong background in high-speed networking systems such as:
o Ethernet Switches
o NPUs
o NICs
o Traffic Managers
o Fabric Switches
o High-performance processors
Skills:
What Were Looking For
Excellent written and verbal communication skills in English.
Strong collaboration skills and the ability to work effectively across teams and disciplines.
Independent, self-driven, and capable of deep technical ownership.
Passion for innovation and cutting-edge technology.
Highly motivated with a proactive mindset.
This position is open to all candidates.
 
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חברה חסויה
Location: Haifa
Job Type: Full Time
Required MI Software Principal Architect
Job Description Summary
As the Molecular Imaging (MI) Principal Architect, you will lead the software architectural vision and execution for MI PET and SPECT systems. This role is pivotal in shaping the software architecture that powers MI products, ensuring they are scalable, secure, and clinically impactful. You will collaborate across engineering, systems, and clinical teams to deliver differentiated solutions that advance diagnostic precision and operational efficiency in nuclear medicine.
Key Responsibilities:
Architecture Leadership & Execution:
Own and drive technical architecture discussions across MI software subsystems and products.
Define and evolve the architecture for MI software platforms, balancing legacy integration with modern design principles.
Develop and maintain architectural roadmaps aligned with MI product strategy and clinical needs.
Ensure software architectural decisions are translated into implementable designs and consistently realized across development teams.
Review and approve critical design decisions and system-level tradeoffs.
Participate in architecture governance and ensure compliance with design controls and regulatory standards (e.g., IEC 62304).
Technology Strategy & Innovation:
Evaluate and integrate emerging technologies into MI software solutions.
Drive software modernization efforts.
Collaborate with the Imaging Architect Office and MI systems teams to define the long-term technology runway for PET/SPECT modalities.
Lead the design, implementation, and governance of safe, compliant agentic AI use across the organizations software development life cycle.
Cross-Functional Collaboration:
Partner with MI systems engineering, clinical applications, and hardware teams to ensure cohesive system-level architecture.
Guide early-stage stakeholder engagement and support integration with legacy and future-state systems.
Influence and align global teams on architectural direction and technical standards.
Operational & Business Acumen:
Ensure architectural decisions support operational stability, serviceability, and lifecycle cost optimization.
Translate architectural strategies into measurable business and clinical outcomes, and communicate effectively with cross-functional stakeholders.
Support capital and operational planning through informed technology choices and risk assessments.
Mentorship & Talent Development:
Mentor staff and engineers within the MI software team, fostering architectural depth and leadership growth.
Contribute to the development of the technical career path and talent pipeline within the MI organization.
Requirements:
Required Qualifications:
Bachelors Degree in Computer Science, Software Engineering, or a related field.
Minimum 15 years of experience in software engineering and architecture, building software for medical equipment products.
Proven experience architecting complex, distributed systems in a modality-specific context.
Strong interpersonal and change management skills.
Ability to set technical direction, mentor engineers, influence and build consensus across organizational levels.
Desired Characteristics:
Experience with high-performance and real-time systems, including GPU-based computation.
Proven ability to design for secure AI use.
Deep understanding of molecular imaging workflows (acquisition, reconstruction, and image processing).
Strong knowledge of healthcare interoperability standards (DICOM, HL7).
This position is open to all candidates.
 
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לפני 1 שעות
Location: Hod Hasharon and Haifa
Job Type: Full Time
Required Computing Network & System Architecture Group Leader
In this role, you will be responsible for several teams of architects, engineers and software developers, all working together to conduct state-of-the-art R&D in system and network architecture. As the group lead, you will guide and mentor the individual team leads, and also conduct hands-on work leading architecture, technology innovation and technical planning and of high-performance computing cluster network, which oriented at AI, HPC, and big data.
Responsibilities:
You will perform a wide range of duties including:
Architecture Innovation:
Deeply analyzing the advantages and disadvantages of mainstream network systems, to find opportunities for network architecture innovation;
Insight into the technology developing trend of the high-performance computing network field, and leading the corresponding technology planning.
Exploring new architectures of high-performance computing network systems and efficiently integrating communication library, topology, and network protocol to solve performance bottlenecks.
Technical breakthroughs in networking and cluster routing algorithm:
Analyzes computing cluster network performance and leads the development of computing cluster network technologies
Research and optimize the heterogeneous interconnection topology of key computing chips to continuously improve the key competitiveness of Huawei computing heterogeneous chipsets
Responsible for the research of data center network technologies, and guide network topology design and routing algorithm development
Group leadership:
Lead the development of a comprehensive system architecture for AI Fabric and HPC Fabric solutions
Manage and mentor highly skilled team leaders, to ensure that the group operates together in pursuit of common goal
Foster a collaborative and innovative work environment
Provide technical guidance and support to team members
Collaborate closely with cross-functional teams internationally, including hardware, software, and ucode design teams, to ensure alignment of architectural decisions with product and platform common objectives
Initiate and supervise collaborations with top academic researchers in Israel and abroad
Stay up to date with emerging technologies and industry trends in AI, HPC and big data industries
דרישות:
At least 10 years of hands-on experience in system architecture design, or equivalent research experience
Demonstrated experience in leading R&D team
Familiarity with high-performance computing cluster services and system architectures, such as AI, HPC and big data.
In-depth understanding of computer networks, communication libraries, and design of AI or HPC cluster networks
Key qualifications you hold include:
Ability to work in a team environment; actively seek out resolution to issues with the team and work co-operatively to build a coherent system; Team-working and excellent inter-personal communication skills.
High level of self-reliance and an autonomous target-oriented work style, can do attitude, eager to learn new things and ready to think outside the box
Ability to work on a schedule, even for un-schedule-able issues such as inventiveness
Experience with network system of AI, HPC or big data cluster
Demonstrated capability in several items from the list below:
o Deep understanding of computer network protocol and network topology of computing cluster
o Familiarity with communication library, such as OpenMPI/NCCL
o Extensive experience in leading the network architecture design of computing cluster
o Experience with implementing routing algorithm
o Familiarity with network specifications of CPU/Network Processing Unit/ Neural Processing Unit/Switch chip
Fluent in written and spoken English
Advantage:
You hold a Doctors degree or above in the field of computer science, electrical and electronic engineering or in a similar background in Research & Development
Publications in reputed jou המשרה מיועדת לנשים ולגברים כאחד.
 
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לפני 1 שעות
חברה חסויה
Location: Hod Hasharon and Haifa
Job Type: Full Time
Required Modeling
Job Description
Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities:
Modeling of HW specification of new architecture and microarchitecture. Working closely with architect and microarchitecture on modeling the specification.
Requirements:
Skill Requirements:
Experience in HW modeling using systemC, including all stages of backend flow: synthesis and power measurements.
Experience with working in a team with various discipline.
Having good communication skills.
Hands on and self contained.
This position is open to all candidates.
 
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לפני 1 שעות
חברה חסויה
Location: Hod Hasharon and Haifa
Job Type: Full Time
Required CPU Core Micro Architect
Job Description
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.
Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Good understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store units, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory controller.
Good understanding of high speed digital VLSI design flow and methodology
Understanding of trade-offs between power, performance and area appropriately to meet the requirements of the product.
At least 6 years of experience in one of the leading CPU companies
Familiarity with the ARM\IA architecture and the micro-architecture for current ARM\IA CPU cores.
Software development (C, assembly).
Hands on experience as a Front end ASIC designer
DESIRED
Co-operate and communicate well with the architecture team and other members of the development.
Excellent verbal and written communication skills.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.
This position is open to all candidates.
 
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