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We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation Infiniband and NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the Infiniband and NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

The architect should have experience in developing models for simulations, analyzing simulation results and development of optimization algorithms.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for a Experienced SW Embedded engineer.
Responsibilities:
Engage with customers, architecture, and product teams to define the right features and solutions to our product portfolio.
Design and implement features optimized for our flagship IoT products, specializing in low-memory and low-power consumption.
Drive end-to-end development of features, ensuring performance, power consumption, reliability, and maintainability.
Collaborate closely with cross-functional teams, including Software, System Validation, Architecture, and Product, to deliver high-quality solutions.

We are seeking a Senior Deep Learning Researcher for an excellent opportunity! This role provides an outstanding opportunity to engage in groundbreaking innovation and contribute to advancing diffusion-based technologies. You will work with pioneering methodologies and tools, crafting solutions that push the boundaries of AI capabilities.

What you'll be doing:

Invent and build ground-breaking techniques for efficient multi-modality model creation and publish the findings in leading journals and conferences.

Combine traditional diffusion technologies with the latest and greatest LLMs.

Contribute to our AI enterprise software to ensure robust and scalable solutions.

Collaborate with internal and external teams worldwide to drive research and development in multi-modal learning, using different professions and resources across the company.

Partner with leading scientific organizations and industry pioneers to remain at the forefront of technological advancements and integrate the latest innovations into practical applications.

Our Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of our Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on performance, power and quality. Modern Clocking design needs to balance high frequency clocks with power, DFx, noise, circuit and physical design constraints.

What you will be doing:
Working on next generation of Networking Switch, NIC and SoC products.
Micro architect and design next generation clock topologies and modules.
ASIC Clock scheme definition.
Improve Power, Performance, and Area (PPA) of state-of-the-art chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
Collaborate with Physical design and timing team to evaluate Clocking concerns and come up with solutions for supporting high speed Clocking.
Understand physical aspects of the chip and develop enhanced clock distribution techniques.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Support Post-Si debug, characterization and productization activities.

We are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:
Join accelerators IP group in Beer-Sheva/ Tel-Aviv, working on RiscV platform unit and cache coherence IP.
design for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work might involve any or all aspects of chip development: uarch , Design.
Work closely with Firmware and other groups around the globe.

We are looking for a System validation site manager.
Responsibilities:
- Lead and manage the system validation group at the IL site.
- Develop and implement validation strategies and plans for Sony products.
- Oversee the operation and maintenance of worldwide automation testing systems.
- Design, implement, maintain, and run automation campaigns on various setups on a weekly/monthly basis.
- Analyze and debug test results, report results and issues into Sonys data systems.
- Ensure compliance with industry standards and regulatory requirements.
- Collaborate with cross-functional teams to ensure seamless integration and validation of new products and features.
- Provide technical guidance and mentorship to team members.
- Improve efficiency by using AI technology
- Design and implement quality procedures

We are looking for a Verification engineer.
As a SOC Verification Engineer, you'll develop complex verification environments for advanced 5G IoT and AI semiconductor products. Working directly with design and software teams, you'll lead verification efforts from block-level to full chip integration. Your work ensures the quality and reliability of innovative systems that power millions of connected devices worldwide.
Create and implement comprehensive verification strategies for complex SoC designs
Develop sophisticated test environments using industry-standard methodologies
Lead verification planning from test definition through coverage closure
Debug complex integration issues alongside design and software teams
Build and maintain reusable verification components
Develop and upgrade our evergrowing verification infrastructure.
Guide junior team members and share technical expertise

We are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What youll be doing:

Work in a combined design and verification team that develops front-end design for the Switch silicon, GPU and HCA.

Plan and Design Verification units/blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, and FWinteraction with organization-wide groups.

We are seeking best-in-class ASIC Design Engineers to design and implement the worlds leading CPU's and SoC's. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What you will be doing:

Participate in micro-architecture development and document specifications.

Implement in RTL and work with the verification team to ensure that the design is functional.

Apply logic design skills to optimize and meet performance and power goals.

Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable and physically implementable design.

We are excited to announce that the team is undergoing rapid growth, and we have opened multiple positions for Junior C++ Software Engineers!
Location: Caesarea, Israel
Your Impact:
You'll develop Core Software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.
In this role, you will:
Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed

We are looking for a Physical Design Team Leader.
What You'll Do
You'll be joining our Physical Design team, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

We are looking for a Senior DFT Engineer.
As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.

We are looking for a Senior CAD Physical Design Engineer.
WHAT YOU'LL DO:
You'll be joining our Physical Design team , which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.