לוח משרות דרושים

Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.

As an Analog Design Engineer, you will:
Design and develop high-speed analog/mixed-signal circuits for industry-leading CMOS process nodes.
Lead all design stages, from architecture definition to final layout sign-off.
Perform circuit simulations, analysis, and debugging to ensure robust performance and reliability.
Collaborate with system architects, digital designers, and layout engineers to optimize circuit performance, power, and area.
Engage in post-silicon validation, debugging, and optimization to enhance circuit functionality.

Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements.
Perform scan verification at Register-Transfer Level (RTL) and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.

Our Silicon One team is undergoing rapid growth, and we are looking for a Release Engineer to join our DevOps team.

Join the Silicon One team developing a unified silicon architecture for web-scale and service provider networks. Our silicon team provides an outstanding, unique experience for ASIC and Software engineers by combining the resources offered by a sizable multi-geography silicon organization with the startup culture and breadth of growth opportunities that working in a smaller team can provide.

Your Impact:
You will play a critical role in overseeing the software release lifecycle, ensuring that software products are delivered efficiently, on time, and within scope.
This position requires a blend of software development expertise and program management skills to coordinate cross-functional teams and manage the complexities of software releases.
Youll be the primary contact point between technical teams and stakeholders, providing regular updates on release status, issues, and resolutions.
As a part of your job, youll also work on continuous Improvement: analyzing release processes and performance metrics to identify areas for improvement, designing and implementing automation processes to enhance efficiency and effectiveness.

Define, develop and execute post-silicon validation content on both pre-silicon setups and real silicon platforms in the lab.
Drive silicon from being a chip towards becoming a product.
Debug and investigate issues along cross-functional teams such as Firmware (FW), Software (SW), Design, DV, ARCH and multiple production teams.
Provide quality functional coverage for Google designs.

We are seeking an experienced Python Developer to join our brilliant team. This position is perfect for a creative software Developer who possesses a passion for inventing and designing software, along with a curiosity and desire to learn.
Responsibilities:

* Develop core software: Utilize your software engineering skills to contribute to our dynamically growing organization.
* Join one of our core development teams and collaborate with our brilliant engineers in creating a unique, scalable, distributed Storage system both on-premises and in the cloud.
* Participate in the full product cycle, from definition to resolving critical customer issues.

You will join our Silicon One team, the epicenter of our ASIC design.

Our engineers handle every aspect of chip design, from definition and architecture to coding, physical design, and signoff.

Your responsibilities will include:
Spearhead innovative switch system design, guiding the process from concept through to mass production.
Collaborate with multi-functional teams in areas such as board design, mechanics, thermal, PCB layout, production, software/firmware, RTL, and more.
Act as the technical focal point and decision-maker for the project.
Conduct hands-on testing in a lab environment and support production and qualification stages.
Define product specifications, develop electrical schematics, and guide component selection and layout processes.

The NPI Product Engineer leads the transition from R&D to operations with a focus on SMT processes. This role leads the introduction of new products and supports existing manufacturing operations. The engineer oversees multi-functional collaboration, supplier management, and test equipment projects. Responsibilities include leading product documentation, conducting ECO processes, and implementing FAIs for SMT components. The position requires validating manufacturing processes and providing training in SMT techniques.
You'll be joining our Silicon One team which is the center of our ASIC design.
Our engineers deal with all chip design aspects: from definition, architecture, coding to physical design and signoff.

Lab post silicon electrical characterization very high speed interfaces characterization and compliance to spec, silicon electrical validation including power, speed, process, packaging thermal and more.

High usage with lab high speed / RF equipment and automation.

We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.

Join the Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Our silicon team provides an outstanding, unique experience for ASIC and Software engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, café, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.

Your Impact:
As a part of your everyday work, youll monitor the performance and health of CI/CD systems, promptly identifying and addressing anomalies to ensure optimal operation. You will also perform initial assessment and troubleshooting of system breakages or failures, determining the root cause and escalating issues to appropriate teams when necessary.
You are going to develop and implement automated monitoring and analysis processes to improve efficiency, reduce manual intervention, and enhance the accuracy of system health assessments.
Collaborate with development teams to define and maintain the testing scope, ensuring comprehensive coverage and alignment with project requirements. You'll be responsible for introducing new testing stages as needed to adapt to evolving project needs and improve testing effectiveness.
Work closely with cross-functional teams to integrate new testing tools and methodologies, fostering a culture of continuous improvement and innovation in testing practices.

Join the Silicon One team in developing a unified silicon architecture for web-scale and service provider networks.
Our silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, café, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.

Your Impact
Define our Silicon One devices and deliver specifications to other development teams.
Work with internal and external customers to understand and define current and future requirements.
Innovate at all levels to deliver market-first features and solutions.
Conduct in-depth research to shape the architecture of next-generation networking devices.
Contribute to full-chip integration and cross-functional collaborations to enhance design methodology.
Participate in the definition and analysis of networking system solutions, ensuring they meet market and technical needs.

Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data centers.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), ATPG).
Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

Youll be joining the post silicon validation team in PHY system group in our group as part of the silicon development.

Our team deals with PHY and system aspects of the device: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the Automation Infrastructure and tools.

We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

Create software solutions that improve the hardware post-silicon testing process through automation. This includes, but is not limited to, developing and maintaining an ATE program development infrastructure for both production and development environments.
Propose, design and implement software automation that directly addresses bottlenecks in today's post-silicon test flow, from DFT to ATE.
Work directly with a Hardware team on projects - prototype and then deploy tools to make a positive impact on Google's chip hardware development process.
Participate in, or lead design reviews with peers and stakeholders to decide amongst available technologies.
Review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).

Own the electrical aspect of integrating advanced Physical Intellectual Propertys, such as Phase-Locked Loops, Serializer/Deserializer, Double Data Rate and General-Purpose Input/Outputs into our Security Operations Center.
Run advanced electrical analysis using HSpice/other circuit simulators.
Generate electrical models for chip and package co-design.
Own chip/package electrical analysis, timing, voltage and noise design budgeting and creation of package design templates, guidelines and sign-off criteria.
Drive package trial layouts for the purpose of physical\electrical aspects investigations, and run deep and thorough electrical analysis in the Lab using advanced measurement equipment.