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we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
perform advanced static timing analysis (sta) for hsio at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.
ai use for timing optimization and data analysis.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
you will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.
we expect you to run, debug, and approve physical verification flows across multiple projects, ensuring strict adherence to our high standards.
you will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.
we are widely considered to be one of the technology worlds most desirable employers. we have some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!

description
we are a global leader in control systems for quantum computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago. at qm, we provide the worlds most leading researchers and organizations with the critical tools they need to develop useful quantum computers. qms hardware and software represent a new paradigm for controlling quantum computers, from a single qubit to hundreds and thousands. we are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. our company is backed by globally recognized venture capital sponsors, including tlv partners, battery ventures, red dot capital partners, avigdor willenz investment group, harel insurance, and others.
we are looking for an excellent failure analysis practical engineer to join our team and build qms state-of-the-art control and orchestration platform. she or he should be a talented and motivated person, who is a real team player, and which can collaborate closely with other engineers from different disciplines and quantum physicists.
the production site is in migdal haemek ( Flex ).
responsibilities:
yield monitoring and improvement
analyze hw failures to a component level in both digital and analog domains.
identify failure trends
rma process handling
failure reports & closure

Are you ready to power the future? At our company, we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery Storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond.?What will you be doing?
* Lead the process control for complete life cycle of the product.
* Verification of ECO/DEV on the production floor and production system.
* Participate in and/or champion
* performance improvement team as required to address machine/process related issues.
* Assist in the training of Operators in the theory of operation and maintenance of production equipment and related systems.
* Perform non-routine assignments of substantial variety and complexity.
* May innovate new approaches or make recommendations for the improvement of manufacturing processes.
Country:
Israel
City:
Ziporit

we are a global leader in the development and manufacturing of advanced infrared detectors and electro-optical solutions for defense and commercial applications.
We are seeking a skilled board designer with extensive experience in high-speed digital design to join our Board Design R&D Team. In this role, you will define system and hardware requirements, design FPGA-based hardware platforms, and validate high-speed interfaces such as DDR4, USB3, Ethernet, MIPI, and Camera Link. You will work closely with firmware, software, and mechanical engineers to deliver robust, production-ready Embedded systems for advanced electro-optical products.
Key Responsibilities
Define hardware requirements and prepare detailed design documentation for FPGA-based boards, including power architecture, configuration, and peripheral circuitry.
Develop schematics and oversee PCB layout for complex, high-speed multilayer boards.
Perform hardware simulations and signal analysis using tools such as LTspice and Cadence.
Design and validate high-speed interfaces including DDR4, USB3, Ethernet, MIPI, and Camera Link.
Define and manage PCB stack-ups, impedance control, differential pair routing, and high-speed layout constraints.
Conduct Signal Integrity (SI) and Power Integrity (PI) analysis to ensure performance, robustness, and reliability.
Lead prototype bring-up, testing, and debugging using lab equipment (oscilloscopes, logic analyzers, VNAs).
Collaborate with firmware, software, and mechanical teams to ensure full system integration.
Participate in design reviews, DFM/DFT processes, and continuous design improvements.
Support production and NPI activities, and resolve hardware-related manufacturing issues.