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We are now looking for a Power Optimization and Analysis Engineer! We prides ourselves on having energy-efficient products. We believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. As part of the u/arch team in the Switch group, you will be responsible for analyzing full chip and unit-level power data and driving the FE/BE ASIC teams to improve their units power efficiency; you will be responsible for researching, developing, and deploying methodologies to help our products become more energy efficient. Key responsibilities include developing techniques to model, analyze, and reduce power consumption of our Switches product line.

As a member of Switch u/arch Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for our next generation switches. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.

What You'll Be Doing:

Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.

Develop and share best practices for performing pre-silicon power analysis.

Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.

Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.

Select and run a wide variety of workloads for power analysis.

Prototype new architectural features in Verilog and power analysis.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.
You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.
Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip
Collaborate closely with Physical Design team to insure a full power integrity
Be responsible on IR architecture for timing convergence
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)
Understand root-cause analysis for voltage drop violations and EM risks
Be responsible and go-to person for any IR related issues.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.
Key Responsibilities
Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient.

We are now looking for a verification engineer for our FC Switch Silicon team. As a FullChip verification Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a FC verification team within the Switch silicon.

Dynamic verification environments planning for units infrastructures and system level.

Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

Responsible to drive the FullChip verification execution, including staging plan of the projects and deliveries.

Our Networking System Product Engineering group is looking for an excellent Software Engineer. The position requires an understanding of HW and SW to provide stable, efficient, smoothly running production tests, to enable high availability, while ensuring the quality of the products being shipped to customers. You will lead the development of our products and raise the bar of the software development quality in the group. We have crafted a team of extraordinary people, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.

What youll be doing: 

Design and develop automated tests for networking Switches and Adapters while working closely with the HW, ASIC, and SW Engineering teams to achieve a reliable test with high coverage.

Exposed to various aspects of design, DFT, and test of our next-generation network products.

Take a significant part in the definition and development of tests from the development level to the final test of Network-Systems.

Utilize test suites to find, debug and resolve problems with production process.

Ability to drive projects to full execution in time and working under pressure of schedule and multi project environment.

Supporting and fixing bugs of existing code. Supporting production lines for: deployments, patches, maintenance.

Test Verification and Validation (both HW and SW). Troubleshooting and streamlining/optimizing our testing procedures.

You will participate in implementing a new strategic platform offering Generative AI (Gen AI) capabilities such as inference, fine-tuning, data curation, data labeling, and more.
We are seeking a highly skilled AI Engineer to design, develop, and deploy state-of-the-art, scalable, efficient Gen AI solutions. You will be part of a high-performing engineering team that values collaboration, innovation, and teamwork. This role is perfect for someone who thrives in an environment where ideas are shared, challenges are met together, and success is a collective achievement.
Responsibilities
Designed and implemented Gen AI platform components using Python and modern microservices.
Drive engineering and operational excellence and best practices.
Collaborate with tech, product, program, and business peers to deliver customer value and drive product vision.
Drive the end-to-end development of AI systems, from research and experimentation to deployment and scaling
Analyze complex problems and identify and define the requirements to solve them.
Stay updated on the latest Gen AI trends and technologies, bringing fresh ideas to the team
Develop according the best AWS practices.

We are seeking an experienced Senior Firmware Engineer to join our NIC Firmware Core team, with a special emphasis on simulation for network adaptors and verification infrastructure. Youll be part of a forward-thinking team dedicated to advancing the tools and frameworks that are used to develop the cutting-edge networking adapter technologies. Your role will be to drive the success of our current and upcoming networking devices by working across various platforms, including C++ object-oriented simulation, verification frameworks and C layer interfacing hardware and firmware.

What Youll Be Doing:

Take part in implementing and assimilating frameworks for Design and Verification both for real-time and simulator environments.

Addressing and solving automation and performance challenges.

Collaborate with chip design, software, and architecture teams to define and craft legacy and new firmware flows.

We are seeking a highly skilled and motivated AI Developer to join our growing R&D team. In this role, you'll design, develop, and scale our next-generation backend platform, AI-driven workflows, and GenAI applications. You'll work with modern cloud technologies and LLMs to build resilient, high-performance systems while contributing to architecture, technical leadership, and mentoring.
This role is ideal for an experienced backend engineer who enjoys solving complex technical challenges, building scalable systems, and working with cutting-edge AI technologies.
Key Responsibilities
Design and develop scalable backend services using Python.
Build resilient distributed systems, microservices, and AI-driven workflows.
Integrate Large Language Models (LLMs) using AWS Bedrock and other AWS services.
Design and implement event-driven architectures and modern APIs.
Optimize databases, search capabilities, and caching strategies to support high-performance applications.
Contribute to cloud infrastructure, CI/CD pipelines, and observability practices.
Collaborate with Product, Data Science, and Engineering teams to deliver scalable solutions.
Provide technical leadership through architecture discussions, mentoring, and hands-on development.

we are looking for a Cloud DevOps Engineer. You will build and deploy complex cloud environments for customers using innovative automation tools and cutting-edge technologies.
As a Cloud DevOps Engineer, you will be responsible for setting up, maintaining, and evolving the AWS cloud architecture, as well as for supporting infrastructure monitoring and alerting, issues troubleshooting, and developing required automation for our customers .
Responsibilities
Assist in creating a tailor-made architecture.
Deployment of advanced services on the cloud.
Implement automation solutions.
Maintain a feedback loop with the companys customers to ensure deliveries are in accordance with the customers needs and expectations.
Debug, troubleshoot and fix technical issues.
Setup large-scale monitoring and logging solutions.

Were looking for people who are relentlessly curious and committed to continuous learning. AI is reshaping every function across our business, and we enable every team member, regardless of role or level, to build fluency in AI tools and concepts. Those who thrive here actively seek out new solutions, experiment thoughtfully, and apply what they learn to drive better, faster, smarter outcomes.
As a Staff AI Engineer, Prompt, you will be tasked with driving the mission of Prompt Security by SentinelOne, where we empower organizations to safely harness the transformative power of Generative AI. As part of our one-stop security platform, you will help provide visibility, governance, and real-time protection against all GenAI concerns, enabling organizations to innovate and prosper in the age of AI without compromising on security. As the Generative AI security field continues to expand, SentinelOne is at the forefront of this revolution. This market's rapid growth demands agility and flexibility from our team. In your role as a Staff AI Engineer, you'll navigate an exciting landscape where innovation is constant, working on the frontline to develop and refine our security engine. We're looking for a builder at heart, someone who learns by shipping, gets hands-on with the latest AI tooling, and thrives in fast-paced environments. If you're passionate about staying ahead in a dynamic market and have the skills and agility to keep pace with its evolution, this is your arena to shine.

We are looking for an experienced Firmware Engineer to join the NIC Firmware team at the Yokneam site. The Firmware team develops cutting edge networking features for cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced.

What you will be doing:

Work closely with the architecture and different software design teams.

Implement new features in the core of our NIC firmware in pre and post silicon environment.

Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.

Gain a deep understanding of system debug, networking technology and stacks, as well as the HW/FW/SW relationship.

You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed.

Were looking for people who are relentlessly curious and committed to continuous learning. AI is reshaping every function across our business, and we enable every team member, regardless of role or level, to build fluency in AI tools and concepts. Those who thrive here actively seek out new solutions, experiment thoughtfully, and apply what they learn to drive better, faster, smarter outcomes.
As a Windows C++ Engineer - Windows Endpoint, you will be tasked with building and maintaining core usermode infrastructure for our Windows agent. This role requires a background in systems programming and strong experience working with complex infrastructure. You will join our Usermode Infra team, which owns the core usermode infrastructure behind our Windows agent, including configuration, asset management, add-ons, and backend communication.
In this role, youll collaborate with talented engineers to drive features end-to-end, contributing to key architectural components. Your work will have a direct impact on millions of endpoints within a core area of our EPP/EDR platform.

We are seeking an experienced Senior Software Engineer to join our NIC Firmware Core team, with a special emphasis on simulation for network adaptors and verification infrastructure. Youll be part of a forward-thinking team dedicated to advancing the tools and frameworks that are used to develop the cutting-edge networking adapter technologies. Your role will be to drive the success of NVIDIA's current and upcoming networking devices by working across various platforms, including C++ object-oriented simulation, verification frameworks and C layer interfacing hardware and firmware.

What Youll Be Doing:

Develop a network adapter simulator that will be used for both development and testing of pre-silicon networking features.

Take part in implementing and assimilating frameworks for Design and Verification both for real-time and simulator environments.

Addressing and solving automation and performance challenges.

Collaborate with chip design, software, and architecture teams to define and craft legacy and new firmware flows.