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As a Senior Software Principal Engineer, you will be responsible for developing sophisticated systems and software based on the customers business goals, needs, and general business environment, creating software solutions.

You will:

Develop end‑to‑end storage features for the Lightning product, driving technical execution from requirements through design, implementation, testing, and deployment
Architect and build AI‑driven infrastructure systems, breaking down complex initiatives, identifying dependencies and risks early, and defining software specifications with a strong security and quality focus
Set the technical bar through hands‑on development and code reviews in C++, Python, and Linux environments
Collaborate with and influence global teams, communicating technical decisions, progress, and risks clearly, while contributing actively in an Agile development environment
Establish and evolve engineering standards and best practices as the organization scales

As a Principal Software Engineer, you will:

Design, develop, and own complex software features - from requirements and design through implementation, testing, and long-term support.
Build high-performance datapath software on SPDK, integrating emerging drive, enclosure, and protocol technologies.
Own performance analysis of the storage software data path - including queueing behavior, CPU efficiency, memory usage, PCIe bottlenecks, and latency behavior.
Work closely with architecture, hardware, and software teams on HW/SW interface definition.
Experiment with and integrate emerging AI tools into the development workflow to boost productivity and innovation.

As a Principal Software Engineer, you will:

Design, develop, and own complex software features - from requirements and design through implementation, testing, and long-term support.
Build high-performance datapath software on SPDK, integrating emerging drive, enclosure, and protocol technologies.
Own performance analysis of the storage software data path - including queueing behavior, CPU efficiency, memory usage, PCIe bottlenecks, and latency behavior.
Work closely with architecture, hardware, and software teams on HW/SW interface definition.
Experiment with and integrate emerging AI tools into the development workflow to boost productivity and innovation.

Were looking for a talented Game Developer to join our studio in Haifa - a gamer at heart who combines strong technical skills with a genuine understanding of what makes games fun, satisfying, and engaging. The ideal candidate can take a game from an early concept or prototype to a polished, production-ready experience, thinking beyond implementation to gameplay, pacing, feedback, animation, UX, and game feel.

Our main focus is HTML5 game development, with games distributed across multiple web and gaming platforms.





Responsibilities
Build and iterate on core gameplay mechanics, game systems, UI, and player interactions, with a strong focus on game feel and responsiveness.
Bridge art and code by implementing animations, visual effects, transitions, and other technical-art elements that bring the game experience to life.
Work closely with artists to integrate and optimize visual assets while maintaining high visual quality and performance.
Rapidly prototype and iterate on gameplay and visual ideas, turning creative concepts into polished, production-ready experiences.
Take ownership of features and game systems, including debugging, performance optimization, and cross-platform compatibility.
Collaborate with game designers, artists, and product managers, while contributing to reusable tools and systems across the studio.
Contribute to technical decisions, development practices, reusable systems, and tools across the studio.

You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

As a Technical Leader, you will be at the forefront of advancing Tetragons capabilities. You will guide architectural direction while staying deeply engaged in building the systems that power our platform. Your impact will span designing high-performance data pipelines, optimizing database and distributed system performance, and ensuring massive streams of system events can be ingested, aggregated, and distilled into meaningful intelligence.

You will collaborate closely with teams across Cisco, including Hypershield and Splunk, to create the integration points that transform raw data into actionable insights for enterprise security. In this role, youll solve some of the most complex system-level challenges in observability and infrastructure, helping Tetragon evolve to meet the needs of modern cloud-native environments.





What youll do:

Develop high-quality Go (and eBPF) code for the Tetragon project.

Design and implement new Tetragon features to enhance its capabilities for Runtime security detection and enforcement

Design and optimize systems for large-scale Tetragon deployment and operation in K8s or VM platforms

Architect infrastructure that converts raw event data into intelligence streams with minimal performance overhead.

Contribute to open-source projects and represent Cisco Isovalent in community discussions.

Participate in architecture reviews, code reviews, and documentation.

The Design for Test (DFT) team is part of the design group, which focuses on logic design, RTL development, and running verification tests.

Their main role is to design test structures embedded within the chip to ensure proper functionality after manufacturing.

The goal is to detect potential manufacturing defects with maximum efficiency and filter out faulty units before they reach the market.



What You'll Do

Insert DFT logic, perform synthesis, and run Automatic Test Pattern Generation (ATPG) to ensure hardware testability.

Execute Gate Level Simulations, timing checks, and DRC checks to maintain rigorous design integrity and performance standards.

Run regressions and perform deep-dive debugging on simulation failures as part of the core verification process.

Work in a small, agile team with an intimate atmosphere that offers direct mentoring and broad professional growth.

As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

we are looking for a ASIC Engineer
Your Impact
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab

we are seeking a Physical Design Technical Leader.

About Cardo Cardo Systems is a provider of cutting-edge communication and connectivity devices and applications for powersports and outdoor enthusiasts. In 2026, Cardo is proudly unveiling its Beyond Helmet line, the first of its kind in the motorcycle industry, fostering a new age in safety, sound, and communications. After pioneering the world’s first Bluetooth-based wireless intercom headset in 2004, Cardo has been responsible for many of the industry’s innovations, revolutionizing communication, pushing technological boundaries, and enhancing user safety. Now sold in over 100 countries, Cardo is proud to be the world’s leading communication device for groups in motion. ?Cardo Systems is looking for a Junior Hardware Engineer to join our ATE team and play a key role in the design, development, and integration of advanced test equipment for our cutting-edge multidisciplinary products. In this role, you will be involved in hardware board design, validation, testing, and production support while working across a wide range of technologies including analog, digital, audio, RF, and optical systems. You will collaborate closely with Hardware, Firmware, Manufacturing, and Quality teams to ensure reliable and efficient testing solutions throughout the product lifecycle. Responsibilities: Design and develop ATE (Automated Test Equipment) hardware boards and test systems. Integrate and validate multidisciplinary technologies including analog, digital, audio, RF, optics, and power circuits. Work with microcontrollers and embedded hardware platforms. Develop test specifications, test methodologies, and validation procedures. Support production activities, troubleshooting, and continuous improvement of manufacturing test processes. Perform hardware bring-up, debugging, and characterization using lab equipment. Collaborate with cross-functional teams throughout development and production stages. Operate effectively in an AI-driven engineering environment.

As a Technical Leader, youll help build the next-generation platform that brings product portfolio together through an AI-native experience. Youll provide hands-on technical leadership to a growing engineering team in TLV while collaborating with global Cisco teams.

Own the technical direction, architecture, and delivery of end-to-end product capabilities.
Translate product goals into scalable designs and executable engineering plans.
Design reliable distributed systems using relational and NoSQL databases, queues, and event-driven architectures.
Build high-quality, modern web experiences and supporting backend services.
Collaborate with architects, product managers, designers, and global engineering teams on cross-product integrations.
Drive security, scalability, resilience, performance, and observability.
Contribute to the codebase, review PRs, and promote engineering excellence.
Mentor engineers and help build a high-performing team.

Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

we are looking for a C++ Software Engineer
Your Impact

Craft and develop software driving the world's most complex infrastructures

Gain intimate knowledge of world-class silicon and programming models

Work with architecture and design teams to define the next generation of ASIC products being developed