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We are seeking a capable and experienced Algorithm engineer to join our R&D team. The engineer will be part of a team responsible for the core autonomy parts of the product responsible for developing the foundational algorithms that guide our autonomous vehicles. This role is a part of the group that oversees Motion Planning, Decision-Making, Localization, and Control, blending traditional robotics with state-of-the-art AI to solve the most challenging problems in autonomous driving. This is an opportunity to architect and deliver the core autonomy stack for a scalable, mapless L3-L4 system. You will work on cutting-edge algorithms, including Agentic AI and large-scale models, and see your innovations deployed on public roads in our global fleet of cars and buses. Responsibilities Be part of the development of four key domains: Motion Planning and Decision-Making: Oversee the trajectory planner and the decision-making module that sets the context for vehicle behavior. Localization: Guide the development of high-frequency, high-accuracy vehicle state estimation using advanced sensor fusion algorithms. Control: Supervise the design and implementation of the vehicle's lateral and longitudinal controllers. Drive innovation by integrating state-of-the-art (SOTA) methodologies, including Agentic AI, vision language models (VLMs), transformers, multi-agent prediction, trajectory optimization, uncertainty management, and safety-aware algorithms.
* Be part of a group involving multiple engineers, from initial research and prototyping to robust deployment and validation.
* Be part of a group in charge of complex data pipelines, from collection and annotation to model training and evaluation.

We push the boundaries of technology, developing innovative DFT solutions that drive industry-leading programmability, scalability, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation.

Your Impact

As an Experienced DFT Engineer, you will:

Own and drive DFT execution across the full product lifecycle, from pre-silicon design through post-silicon debug and production qualification.

Define and align DFT architecture and strategy in close collaboration with chip architects, design, and verification teams.

Oversee and contribute hands-on to the implementation of DFT features, including ATPG, scan insertion and compression, and memory BIST.

Lead silicon debug activities and root-cause analysis, driving corrective actions to improve yield, reliability, and test quality.

Establish, standardize, and evolve DFT methodologies and best practices across projects.

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Collaborate closely with the ASIC Architecture team to implement an accurate and efficient software model based on the architecture specifications.

Partner with both Software and Hardware design teams, providing support as they use the simulator as the golden reference for hardware implementation.

Ensure the simulator meets the highest standards of performance, reliability, and usability.

Contribute to defining best practices and methodologies for model development, validation, and integration. 

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.