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be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a SOC physical design engineer, you will collaborate with functional design, design for testing (dft), architecture, and packaging engineers. additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.the ai and infrastructure team is redefining whats possible. we empower customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our  users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
define and drive the implementation of physical design methodologies.
take ownership of one or more physical design partitions or top level.
drive to the closure of timing and power consumption of the design.
contribute to design methodology, libraries, and code review.
define the physical design related rule sets for the functional design engineers.

our company is a global leader in control systems for our computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago. at qm, we provide the worlds most leading researchers and organizations with the critical tools they need to develop useful quantum computers. qms hardware and software represent a new paradigm for controlling quantum computers, from a single qubit to hundreds and thousands. we are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. our company is backed by globally recognized venture capital sponsors, including tlv partners, battery ventures, red dot capital partners, avigdor willenz investment group, harel insurance, and others.
we are looking for an excellent design engineer to join our team and build qm's state-of-the-art control and orchestration platform. we are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists
responsibilities:
learning system and sw requirements for proper implementation of hw-sw interface
designing a configurable and very low-latency challenging rtl
bringing the state-of-the-art fpga to its limits with regards to logic & timing optimization
end2end ownership of the entire coding process (arch->uarch->design->implementation)

description
we are a global leader in control systems for quantum computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago. at qm, we provide the worlds most leading researchers and organizations with the critical tools they need to develop useful quantum computers. qms hardware and software represent a new paradigm for controlling quantum computers, from a single qubit to hundreds and thousands. we are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. our company is backed by globally recognized venture capital sponsors, including tlv partners, battery ventures, red dot capital partners, avigdor willenz investment group, harel insurance, and others.
we are looking for an excellent failure analysis practical engineer to join our team and build qms state-of-the-art control and orchestration platform. she or he should be a talented and motivated person, who is a real team player, and which can collaborate closely with other engineers from different disciplines and quantum physicists.
the production site is in migdal haemek ( Flex ).
responsibilities:
yield monitoring and improvement
analyze hw failures to a component level in both digital and analog domains.
identify failure trends
rma process handling
failure reports & closure

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will use application-specific integrated circuit (asic) design experience to be part of a team that develops complex asic system -on-chip ( SOC ) intellectual property from proof-of-concept to production. this includes creating ip level microarchitecture definitions, register-transfer level (rtl) coding and all rtl quality checks. you will also have the opportunity to contribute to design flow and methodologies, including design generation automation. you will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. you will develop/define design options for performance, power and area.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and cloud. our end users are, cloud customers and the billions of people who use services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define the ip microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
perform rtl development (coding and debug in verilog, systemverilog).
conduct function/performance simulation debug and lint/cdc/fv/upf checks.
engage in synthesis, timing/power closure, and asic silicon bring-up.
contribute to verification TEST plan and coverage analysis of block and SOC -level.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a design team manager within the server chip design team, you will use your asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.in this role, you will oversee the intellectual property (ip) and SOC vlsi design cycle from architecture to production. you will own and manage ip, subsystems and SOC development, leading a group of designers and design tech leads. you will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.the ai and infrastructure team is redefining whats possible. we empower our customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our cloud, global networking, data center operations, systems research, and much more.
responsibilities
manage a team of tech leads and designers. develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
lead design activities at ips, subsystems, and system -on-chips (socs).
plan, execute, track progress, assure quality, and report status of the assigned activity.
work closely with internal customers and support multiple activities and deliverables.
assure and manage deliverables quality at all rtl design categories including reviews, static checks, design for physical design, power, etc.

as a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. you develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of google users.
as a cmos technologist and foundry engineer, you'll be part of the growing chip design team. in this role, you'll be responsible for driving cmos (complementary metal oxide semiconductor) foundry partners, intellectual property (ip), and chip design and implementation teams to perform cmos transistor scaling and power/performance analysis (ppa), and producing technology roadmap benchmarks. you will also be involved in interfacing and driving our design ip partners.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
engage with cmos foundry partners, manage foundry design kits and design library collaterals, and work with our design teams to perform ppa simulations on benchmark circuits.
work with fab partners on device and circuit level TEST structures, TEST chips, and characterization and correlation of silicon data. you will use the results of this work to influence design optimizations.
work with ip partners, design, and physical design teams to design advanced cmos.
work with chip implementation and physical design teams on micro-architecture tradeoffs, support design tool flow bring-up, and address all physical implementation details leading to product tapeout.
work with our commercial and product teams on foundry and ip vendor management, track technology roadmaps, and determine appropriate technology and ip integration strategies.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a cpu workload analysis researcher within our company cloud's msca organization, you will be integral to developing silicon solutions powering our company's direct-to-consumer products. you will join a research and development team focused on analyzing and profiling workloads requirements within the company cloud environment. your role will involve conducting in-depth research on cpu optimization, feature development, and ml usages over compute platforms, contributing to identifying key areas of investment and future opportunities. this role offers a unique opportunity to perform groundbreaking research with a significant impact on both research methodologies and industry products, within the server chip architecture team. your work will directly influence the next generation of hardware experiences for millions of our company users and cloud customers.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
plan and execute detailed analysis of cpu workloads within the company cloud infrastructure, analyze trends and map future requirements.
collaborate closely with architecture and modeling owners to understand design specifications and identify critical scenarios related to cpu performance and efficiency.
develop and implement custom workload generation tools and methodologies to simulate real-world usage patterns on our company cloud platforms.
analyze the impact of Machine Learning applications on cpu usage, identifying opportunities for optimization and feature enhancements.
lead the investigation and development of metrics to measure cpu performance and efficiency, presenting findings to stakeholders and contributing to strategic decisions.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
with your technical expertise you will manage project priorities, deadlines, and deliverables. you will design, develop, TEST, deploy, maintain, and enhance software solutions.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are  cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
create software solutions that improve the hardware post-silicon testing process through automation. this includes, but is not limited to, developing and maintaining an automatic TEST equipment (ate) program development infrastructure for both production and development environments.
propose, design and implement software automation that directly addresses bottlenecks in today's post-silicon TEST flow, from design for testing (dft) to ate.
review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).
contribute to existing documentation or educational content and adapt content based on product/program updates and user feedback.
triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, network, or service operations and quality.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.as a power and signal integrity engineer, you will be responsible for the design and characterization of signal and power integrity of our ic designs. you will design the external electrical interfaces of the device, from their signal/power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our ic designs meet systems design budgets and achieve the highest performance. you will work with systems architects, asic design, systems engineers, and partner cross-functionally with teams and external vendors/partners.the ml, systems, and cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
generate precise electrical models (e.g., s-parameters, spice models) for components such as packages, pcbs, and connectors for use in simulations.
simulate high speed interface electrical behavior using hspice or other circuit simulators.
execute lab measurements utilizing TEST equipment like oscilloscopes, vector network analyzers (vna), time domain reflectometers (tdr), spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
establish design rules and guidelines for optimal signal/power integrity during pcb and package layout, ensuring high production yield and reliability.
document design specifications, analysis results, and validation reports to ensure compliance with standards and for future reference, while collaborating extensively with cross-functional teams, including asic architects, digital/analog designers, physical design/layout engineers, and system engineers

in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the schematic capture and component selection for high-density, multi-layer pcbs (20+ layers) incorporating high-power asics (tpus/cpus), fpgas, and high-speed memory (hbm/ddr5).
design and validate high-speed interfaces including pcie gen 6.0/7.0, 400g/800g/1.6t ethernet (pam4). collaborate with signal integrity (si) engineers to define routing constraints and stack-up.
design multi-phase power regulators (vrms) capable of delivering >1000a currents with fast transient response for ai processors.
work with pcb layout designers to guide placement and routing of critical signals and power planes.
lead the lab bring-up of first-silicon/first-board by debugging hardware issues using oscilloscopes, tdrs, and logic analyzers to root-cause failures to component, assembly, or design issues.

Head of Antenna Department About the Role A leading aerospace and missile systems engineering organization is looking for a Head of Antenna Department to lead advanced antenna development activities for airborne systems.
 Responsibilities:
- Lead and manage a team of antenna and electromagnetics engineers, including defining R&D goals, driving technological innovation, developing and mentoring employees, resource planning, task allocation, and prioritization.
- Lead the development of antennas and antenna arrays for communication, navigation, and radar systems on airborne platforms. Manage the full development lifecycle from requirements definition, antenna design, prototype manufacturing, laboratory testing, and antenna range measurements.
- Perform engineering analysis using tools such as CST and MATLAB, including system -level calculations such as Link Budget analysis.
- Lead antenna design activities within projects from the planning phase through production and integration. Manage schedules, milestones, and project deliverables, including writing technical specifications and Statements of Work (SOW).
- Collaborate with cross-functional teams including system engineers, mechanical engineers, quality, procurement, manufacturing, logistics, and IT.
- Manage subcontractors and work with external manufacturers.
- Interface with customers, support production activities, and present technical material in design reviews and technical meetings.

Are you ready to power the future? At our company, we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery Storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond.?What will you be doing?
* Lead the process control for complete life cycle of the product.
* Verification of ECO/DEV on the production floor and production system.
* Participate in and/or champion
* performance improvement team as required to address machine/process related issues.
* Assist in the training of Operators in the theory of operation and maintenance of production equipment and related systems.
* Perform non-routine assignments of substantial variety and complexity.
* May innovate new approaches or make recommendations for the improvement of manufacturing processes.
Country:
Israel
City:
Ziporit