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We are seeking an experienced and self-driven Systems Engineering Functional Manager to lead our systems engineering team for our CT/AMI detection platform (DMS). This team is responsible for the full lifecycle of system-level development from systems design, requirements management, architecture design, execution of technical reviews, setting the integration plan to verification, validation, and regulatory compliance.

Your role:
Lead and mentor a multidisciplinary systems engineering team, fostering growth, collaboration, and technical excellence.
Provide strategic and hands-on technical guidance in the development of CT/AMI detection platforms.
Oversee engineering planning and execution to support complex project ensuring timelines and quality standards are met.
Resource assignment and prioritization including headcount and budget management.
Working across functions and team boundaries to define, design, and implement the next generation of products.
Decision making in cross-disciplinary and architectural aspects.
Drive continuous improvement in engineering and systems engineering processes and tools.
Support audits and regulatory inspections as a subject matter expert.
Represent DMS System Design in global engineering forums and initiatives.

We are looking for a Board Design Engineer to join our team. In this role, you will be responsible for the end-to-end development of hardware boards, including schematic
design, component selection, PCB layout guidance, board bring-up, debugging, validation, and release to production.
Responsibilities:
Design and develop hardware boards for our products.
Create schematics and select components according to system requirements.
Guide PCB layout activities.
Perform board bring-up, debugging, testing, and validation.
Support product release to production.
Work closely with relevant teams throughout the development process.

The ATE Systems Group leads the development of complex, multi-disciplinary capital equipment (software, hardware, optics, mechanics), automated machines designed for the calibration, testing and production of the cutting-edge LiDAR technology.

We are looking for a hands-on ATE System Technician to join our team. As part of the team, youll:

Bring-up multi-disciplinary setups & testers.
Execute complex system integration testing and experiments.
Support testing a variety of company's products.
Tester validation, verification, qualification, and certification.
Interact with multi-disciplinary systems and teams.
Write documentation, test plans, and results (English).

we are seeking an experienced EMC Engineer with the ability to understand complex systems to participate in the Qualification process for its revolutionary products.

What you'll do

Plan, coordinate, and perform EMC testing on full systems and components during the Design and Product Verification phase.
Influence hardware by recommending corrective actions at the PCB and system-level design, providing expert guidelines on grounding, shielding, filtering, etc.
Serve as a focal point in leading the analysis of EMC design requirements and findings at both the system and component levels
Based on collected data, determine if specifications, regulations, customers expectations, and acceptance criteria are satisfied - According to automotive and defense standards
Support the formation of technical reports, and be able to present conclusions to stakeholders

Were looking for an AI Algorithms Manager to lead the development of advanced algorithms in the telehealth domain, with a direct impact on how care is delivered and experienced.
In this role, youll lead a team of algorithm developers, drive algorithmic work end-to-end, from problem definition and data exploration to model development, evaluation, and integration into real-world systems. The work focuses on developing AI capabilities in computer vision, signal processing and LLM domains to tackle complex challenges and turn them into reliable, production-ready solutions.
Key Responsibilities:
Lead algorithmic development end-to-end- from shaping the technical problem and defining data needs to development, architecture, validation, and implementation
Drive innovation and infrastructure initiatives to advance the solution in alignment with the latest scientific progress
Stay hands-on in research and development, actively contributing to core algorithms and solving complex technical challenges
Design, develop, and optimize models using machine learning, computer vision, and signal processing techniques
Guide the work of team members, providing technical directions, feedback, and support
Collaborate with cross-functional teams (engineering, product, clinical) during problem definition, solution design and smooth integration into production systems
Ensure robustness and reliability through proper evaluation, validation, and continuous improvement of models
Promote best practices in development, experimentation, and code quality

Required Staff RTL IP/Component Design Engineer, Cloud
About the job
In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of our platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the block level design document such as interface protocol, block diagram, transaction flow and pipeline, etc.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Support synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Do you want to help us build the DNA of tech.?
we are looking for a Maintenance Electronic Engineer to join our Maintenance Department. You will be for the maintenance of machines and equipment used in the production and distribution process of a company.
Job Location:
Dimona located in the southern part of Israel in the Negev, not far from the Dead Sea area, the lowest location in the world.
What you will be doing:
Maintain, develop, and improve equipment across the production floor.
Collaborate with R&D, engineering, maintenance, and production teams.
Provide service and support to maintenance and production departments.
Designing and developing new equipment (e.g., PCB boards) and participating in discussions.
Writing PLC programs and resolving communication issues.
Supporting equipment post-production transfer.
Enhancing existing equipment to improve efficiency or replace obsolete components.

Required ASIC Design Verification Technical Lead, High-Speed DSP
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Technical Lead, you will define how we verifiy the physical-layer Digital Signal Processing (DSP) pipelines powering our next-generation AI hardware accelerators. You will drive the shift toward Emulation and Post-Silicon Correlation, ensuring that our architectural reference models and pre-silicon simulations perfectly match the physical behavior of the high-speed silicon in our planetary-scale AI data centers.
Responsibilities
Design, build, and scale constrained-random verification environments using SystemVerilog and UVM for high-speed physical-layer DSP blocks.
Build co-simulation frameworks and predictors to compare RTL implementation output against high-level algorithmic models.
Define and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed-point quantization effects, and numerical overflows.
Author dynamic stimulus sequences and virtual sequencers to stress-test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high-frequency jitter profiles.
Lead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification.

Required Staff Design Engineer, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Required Senior SoC Formal Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission at System Infrastructure is to build the best cloud in the world for our services and for Cloud customers, by solving real world business issues of performance, cost, and scale, utilizing hardware, software, and system solutions. To better serve evolving cloud needs, we are establishing a team in Israel to develop custom chips for servers.
In this role, you will perform formal verification of design properties of complex ASIC designs. You will collaborate closely with design and verification engineers to define meaningful properties that capture the design intent of a logic block and constraints on its input stimulus. You will also help define and improve design and verification methodologies that allow you to achieve formal verification closure.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Plan the formal verification strategy and create the properties and constraints for complex digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties and apply sign-off to blocks.
Pioneer and refine formal verification methodologies by systematically embedding AI tools to optimize verification accuracy.
Architect and implement reusable formal verification components.

Required Senior SoC Product Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT.
Drive interactions with wafer fab and OSATs, own and drive checkpoints for key quality metrics.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and RMA handling.
Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including Return Merchandise Authorization (RMA) support.
Collaborate with cross functional teams across the globe including ATE and SLT Test Engineering, Quality and Reliability (Q&R), Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.

Required Senior Silicon DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Requied SoC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. You will be creating SoC Level micro architecture definitions, Register-Transfer Level (RTL) coding and will do all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for test (dft) etc. You will face technical tests and develop/define design options for performance, power and area.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform RTL development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.