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We are looking for an excellent, creative, and independent IC Test Validation & Automation Engineer to join our Networking unit. Our Networking has continuously reinvented itself over the years, delivering industry-leading high-speed Ethernet and InfiniBand solutions that push performance, bandwidth, and reliability from one generation to the next. In this role, you will help transfer our Network Silicon IC products, including Switch, NIC, and SmartNIC devices, from design engineering to high-quality mass production. You will define and automate IC test validation methodologies, develop validation tests and automation infrastructure, and build scalable flows for regression execution, results collection, reporting, and debug.

You will work closely with HW, SW, FW, SPE, SLT, DFT, security, and production teams, and will be responsible for improving test stability, coverage, quality, and debug visibility across wafer-level and final-test environments. The role includes troubleshooting complex test issues, improving validation methodologies, integrating tools such as Jenkins, Git, Jira, and automation agents, and acting as a gatekeeper for IC test program quality before production release. If you are passionate about IC product testing, automation, and enabling the highest-quality Networking products, we would like to hear from you.

What you'll be doing:

Definition and automation of IC test validation methodologies and procedures.

Developing validation tests and automation infrastructure.

Building Jenkins-based flows for regression execution, result collection, and reporting.

Using Git-based development workflows for test infrastructure, reviews, and releases.

Integrating Jira and MCP-based tools into validation, debug, and issue-tracking flows.

Maintaining products quality by improving test stability, coverage, quality, and debug visibility.

Troubleshooting test issues and improving automated testing methodologies.

Our Advanced Development Network Engineer role in Israel offers a special chance to contribute to large-scale network simulations for innovative AI datacenter research and development. You will be part of a dynamic team that values creativity and collaboration. If you are enthusiastic about technology and eager to build a significant difference, this is the place for you!


What you'll be doing:

Developing a brand new digital twin powered by CUDA technology for advanced research on data centers.

Collaborating with a team of extraordinary engineers and researchers to develop and implement innovative solutions.

Partnering with diverse teams to ensure smooth integration and deployment of network solutions.

Continuously exploring new technologies and methodologies to improve our network capabilities.

We help leaders manage tradeoffs and decision making with intelligence powered by AI so they can guide their teams to focus on the right innovations and creativity required to improve the business. And as customers increase AI adoption, we also help them leverage AI responsibly and with governance to ensure software delivery teams and practices dont hinder innovations from AI. 

Our mission is to unlock endless digital possibilities by harmonizing the delivery of software. Our vision is to be THE enterprise platform for AI driven software development.

We are seeking a Software Developer who can see the big picture. This essential role will give you an opportunity to craft and deliver a new class of user-space applications and kernel space drivers. You will join the storage software team. The team is responsible for developing storage drivers & storage emulation solutions.

What you will be doing:

End-to-end responsibility for major features in user space and kernel applications.

Maintain and enhance storage Linux Kernel drivers.

Participate in enhancing our cutting-edge technology storage solutions
Work with partners and customers worldwide.

Drive performance tuning, usability improvements, and test automation.

Our Networking team is looking for an outstanding candidate who thrives in a multifaceted environment, to facilitate managing SW Releases for our leading SW products by taking responsibility for cross projects activities. In addition, ensure releases are delivered on time and in high quality, coordinate between development and testing groups and between global SW groups. The role will require to gain good understanding of products dependencies.

What youll be doing:
Be an effective leader in crafting and driving a delivery of high quality SW in an efficient way.
Collaborate with Engineering, Operations, Architecture and Marketing across the globe to coordinate the release of products and ensure release will meet the schedule and with high quality. In parallel, partner with the QA teams to ensure alignment of all tests between the development, verification and QA groups.
Take full ownership of projects from kickoff to signoff.
Manage multiple parallel releases with strong attention to detail, ensuring clarity, alignment, and consistent communication across teams while tracking dependencies, milestones, and deliverables.
Maintain clear, up-to-date visibility of the release status, ensuring all stakeholders have an accurate understanding of progress, next steps, priorities, and risks at any given time.
Support Senior Release Managers with release activities.
Own and manage selected cross-products topics (e.g., customer bugs, release checklists, RCAs, Triage, define and improve processes).
Conduct release meetings and communicate release status. Resolve issues when they appear and raise red flags when needed. Work with planning and tracking systems to lead the release progress, and build release indicators.

We are seeking a hands-on, results-focused Manufacturing & Production Security Specialist to join our ITPE (Interconnect Product Engineering) organization. You will own and drive cybersecurity standards across production environments and testing lifecycles, spanning networking product lines manufactured at internal and contract manufacturing sites. We develop a collaborative and inclusive work environment, where ideas are shared and innovation is encouraged.

As the ITPE Security Specialist, you will collaborate with Infrastructure Architects and Test Engineering Developers to design, build, and implement a highly secure PKI environment and robust data paths. This role combines deep technical security implementation with governance spanning on-site and outsourced manufacturing locations, ensuring strict security compliance while enabling engineering velocity.

What youll be doing:
Implement, automate, and maintain a robust and secure PKI infrastructure; build secure Key Provisioning and Code Signing workflows within ATE pipelines.
Own lifecycle management of digital certificates and cryptographic identities across all product families (LinkX, switches, NICs).
Partner with test developers to harden the Test Engineer Datapath, preventing data tampering or leakage.
Implement security baselines, endpoint protection, and AD Privilege Management across test stations and MES systems.
Define, enforce, and audit security policies across all internal and external production sites (Contract Manufacturers).
Implement network segmentation between corporate IT, engineering networks, and the manufacturing floor.
Own recurring security syncs and present security status updates to ITPE leadership.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.
As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.
Key Responsibilities
Own and develop formal verification environments from scratch through to sign-off
Apply formal verification methodologies and strategies to prove the correctness of intricate designs
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
Architect and develop generic, common formal functions and properties to be reused across multiple projects.

Our IC Product Engineering are looking for a senior engineer to join us and lead the way we develop characterization and validation methodologies for our next-generation silicon! This role puts you at the center of our hands-on validation work while shaping how we approach characterization at scale for the programs ahead.

What youll be doing:

Define and develop characterization and validation techniques for post-silicon bring up and production test, spanning electrical, functional, and performance characterization. Working in close coordination with test engineering, yield, NPI, FW and other teams, lead methodology planning for future products and serve as the synchronization point between our Israel and US-based teams.

Day to day, this means:
Driving alignment on tooling, flows, and coverage requirements ahead of tape-out and first silicon.
Translating product requirements and silicon behavior into structured characterization plans with clear coverage targets, risk areas, and data collection strategies.
Leading methodology transfer into execution - working with team managers to ensure tooling, methods, and engineers are in place for a smooth handoff.
Identifying methodology gaps early in the program cycle and resolving them through cross-functional collaboration.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.
As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You wont just be using tools; youll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.
Key Responsibilities
Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes
Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows
Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics
Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Package Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world's largest AI clusters.
As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling our company products to operate reliably in the worlds most demanding AI and cloud environments.
Key Responsibilities
Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing
Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met
Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor technical reviews.

1. AI Architecture & Technical Leadership

Guide AI architectural direction across platform, focusing on system design, model lifecycle, and integration of AI components into product workflows.
Act as a senior technical reviewer and thought partner for complex or cross-team AI design decisions.
Provide technical oversight on areas such as exploring new models/technologies/opportunities for the company
Surface architectural risks, tradeoffs, and long-term implications, including cost, security and compliance aspects and clearly advise the VP of AI when certain technical directions should not be pursued.
This role influences judgment, clarity, and experience, not through blocking authority.

2. Hands-on Applied Innovation (Core Pillar | ~50%)

Spend at least 50% of time hands-on, building:
End-to-end AI prototypes
Technical demos and proofs of concept
Exploratory implementations of new AI capabilities
Drive applied innovation that:

De-risks new technologies
Demonstrates feasibility and impact
Informs product direction and business opportunities
Build fast, concrete examples that teams can learn from and extend.
Transition successful prototypes to team ownership for further development and scaling.
This role is expected to lead AI innovation by doing, while working closely with product, medical and engineering

3. Best Practices & Technical Enablement

Define and promote best practices for applied AI development, including:
Rapid prototyping and vibe coding.
Agent design, orchestration, and evaluation patterns
Experimentation, benchmarking, and validation workflows
Help teams align on shared technical patterns, tools, and standards.
Identify opportunities to consolidate duplicated efforts and improve cross-team coherence.
Lead technical deep dives, architecture discussions, and design reviews.
4. AI Compliance & Regulatory Enablement (Technical Scope)

Ensure Navinas AI development practices align with applicable AI regulations for a software product handling sensitive medical data.
Define and guide AI-specific compliance practices, including data usage, transparency, evaluation, and documentation expectations.
Support and contribute to AI-related compliance and regulatory documentation, in close collaboration with Legal, Security, and Medical Research teams.
Serve as a technical point of reference for AI compliance questions.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR CAD to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.
You will continuously develop the Electro-Migration and IR Drop (EMIR) flow, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.
Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) flow
Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate closely with Analog/SerDes designers to integrate current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis flow
Understand root-cause analysis for voltage drop violations and EM risks
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data.

We are looking for best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join accelerators IP group in Beer-Sheva, working on RiscV processor IPs.

Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work might involve any or all aspects of chip development: Verification, Design.

Work closely with Firmware and other groups around the globe.