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our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Lead the development of flows & methodologies from Synthesis, Place & Route & All signoff flows.
Plan & execute flow releases, coordinate & track development tasks between the team.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Serve as the technical lead while mentoring and guiding team members.

Which department will you join? our company's VLSI team - a group designing the EyeQ chips for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering. Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Engineer to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

we are seeking a Real Estate and Asset Management Coordinator to join our team in Rehovot!
Responsibilities:

Managing the municipal asset registry, including operation of a computerized system
Handling contracts and agreements related to real estate assets
Managing land registration processes, including coordination with the Land Registry Office and Israel Land Authority
Analyzing zoning and urban planning schemes and tracking planning procedures related to municipal property rights
Executing land expropriation procedures
Maintaining the municipal land allocation registry

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block or IP owner from RTL to GDS with horizontal domain ownership.
Collaboration with front-end and architecture teams to address issues, define design methodologies and improve QoR & convergence.
End to End ownership from Synthesis, DFT insertion, Floor Planning , Place & Route till signoff.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Exploratio of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Technical support and mentoring the engineers in the team.

our company's EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Layout activities for complex Sub Full Chip with several levels of hierarchies.
Floorplanning, top-down deliveries & bottom up rollup , Sub FC/ IP level integration & verification.
Signoff on all physical design domains PV, IR/EM, LEC, LP Verification.
Physical Verification expert, building, maintaining and enhancing the flow for new technologies, improving reliability & convergence ToT.
Servings as a technical expert while mentoring and guiding team members,
Hands-on physical design block owner from RTL to GDS , an option.

Developing UI for operational systems featuring maps and a geographic situational picture
Leading technical aspects of the Frontend domain
Migrating an existing system to a modern Web environment

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.

we are at the forefront of developing autonomous driving systems. our company state-of-the-art ECUs are integrated into vehicles from leading OEMs and enable its leading autonomous driving solutions. Are you passionate about designing cutting-edge solutions for complex, high-impact challenges? Do you have an eye for detail and a knack for seeing the bigger picture? At our company, our Platform Architecture team plays a pivotal role in seamlessly shaping system architecture into high-performance systems that drive the future of autonomous driving. By joining us, youll collaborate with top engineers to develop innovative systems that not only shape the evolution of our industry-leading products, but also contribute to advancing the future of mobility. As part of our mission, youll play a key role in making the world a safer place through autonomous driving technology.
What will your job look like?
Define System Architecture: Develop system requirements and architecture that align with customer needs and our company's software and hardware products.
Design and define: system architectures and flows for critical functions, including boot processes, power-on sequences, system health monitoring, and diagnostics, ensuring robust and reliable platform performance.
Engage with customers: analyze and understand customer requirements and maximize alignment with existing solutions.
Collaborate with Product Managers: Ensure requirements are in sync with system architecture and that both software and hardware developments meet system-level objectives.
Work closely with Project Managers: Define, map dependencies, and prioritize the scope of customer releases.
Innovate with Sensing, Driving and Fusion teams: to optimize overall system performance.

we are at the forefront of developing autonomous driving systems. our company state-of-the-art ECUs are integrated into vehicles from leading OEMs and enable its leading autonomous driving solutions. Are you passionate about designing cutting-edge solutions for complex, high-impact challenges? Do you have an eye for detail and a knack for seeing the bigger picture? At our company, our Platform Architecture team plays a pivotal role in seamlessly shaping system architecture into high-performance systems that drive the future of autonomous driving. By joining us, youll collaborate with top engineers to develop innovative systems that not only shape the evolution of our industry-leading products, but also contribute to advancing the future of mobility. As part of our mission, youll play a key role in making the world a safer place through autonomous driving technology.
What will your job look like?
Define System Architecture: Develop system requirements and architecture that align with customer needs and our company's software and hardware products.
Design and define: system architectures and flows for critical functions, including boot processes, power-on sequences, system health monitoring, and diagnostics, ensuring robust and reliable platform performance.
Engage with customers: analyze and understand customer requirements and maximize alignment with existing solutions.
Collaborate with Product Managers: Ensure requirements are in sync with system architecture and that both software and hardware developments meet system-level objectives.
Work closely with Project Managers: Define, map dependencies, and prioritize the scope of customer releases.
Innovate with Sensing, Driving and Fusion teams: to optimize overall system performance.