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we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.

we are looking for a data center network deployment engineer to join the networking clusters solutions hpc/ai infrastructure team. we are building supercomputers and ai clusters based on groundbreaking technologies. we are looking for a network/ system Engineer to be a key player to the most exciting computing hardware and software to contribute to the latest breakthroughs in artificial intelligence and gpu computing.
you will work with the latest accelerated computing and deep learning software and hardware platforms, and with many scientific researchers, developers, and customers to craft improved workflows and develop new, leading differentiated solutions. you will interact with hpc, os, gpu compute, and systems specialist to architect, develop and bring up large scale performance platforms. does this sound like you? if so, we would love to hear from you!
what you'll be doing:
deploy, manage and maintain large scale ai data centers - control, network and Storage stack
work with multiple software and hardware teams to optimize the clusters networking health and performance
develop and implement automation scripts for network, compute and Storage operations and deployments
supporting research & development activities and engaging in pocs/povs for future improvements.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
perform advanced static timing analysis (sta) for hsio at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.
ai use for timing optimization and data analysis.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
you will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.
we expect you to run, debug, and approve physical verification flows across multiple projects, ensuring strict adherence to our high standards.
you will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.
we are widely considered to be one of the technology worlds most desirable employers. we have some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!

we are looking for a software engineer networking security team is looking for an outstanding software engineer with strong expertise in Embedded systems and programming in memory-safe languages to drive the integration of memory-safe languages into firmware stack. in this role, you will help define and complete our next-generation firmware development methodologies. youll be responsible for introducing memory-safe practices, shaping language-integration standards, and improving the reliability and safety of our firmware products.
what you'll be doing: drive the adoption of memory-safe development practices across firmware teams.
lead the definition and implementation of a mixed-language sdlc for firmware that incorporates memory safe-languages alongside C.
assist architecture and r&d teams in designing firmware components suitable for implementation in memory safe languages.
perform security reviews of existing C modules and propose migration or refactoring strategies.
provide guidance on interoperability and integration with C, including toolchains, build systems, and runtime considerations.
mentor teams and developers, promoting guidelines for safe, maintainable, and verifiable Embedded firmware development.
serve as a technical focal point across multiple development groups, including hands-on contributions to code development.

description
we are a global leader in control systems for quantum computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago. at qm, we provide the worlds most leading researchers and organizations with the critical tools they need to develop useful quantum computers. qms hardware and software represent a new paradigm for controlling quantum computers, from a single qubit to hundreds and thousands. we are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. our company is backed by globally recognized venture capital sponsors, including tlv partners, battery ventures, red dot capital partners, avigdor willenz investment group, harel insurance, and others.
we are looking for an excellent failure analysis practical engineer to join our team and build qms state-of-the-art control and orchestration platform. she or he should be a talented and motivated person, who is a real team player, and which can collaborate closely with other engineers from different disciplines and quantum physicists.
the production site is in migdal haemek ( Flex ).
responsibilities:
yield monitoring and improvement
analyze hw failures to a component level in both digital and analog domains.
identify failure trends
rma process handling
failure reports & closure