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Requirements:
* 3+ years of Python development (must-have)
* Strong C/C++ and embedded Linux experience
* Experience with Docker / containerization
* Hands-on experience with cameras or sensor integration
* Experience interfacing Linux software with FPGA-based devices
* End-to-end ownership of development, testing, and documentation

Requirements:
Senior RTL Design Engineer (6048) As an RTL Design Engineer, you would be responsible for one or more functional units of the micro-controller and application processor, while working closely with architecture, verification, modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals. An ideal candidate will have at least 6 years of work experience in microprocessor, SOC, memory controller and interconnect IP design. Additional Job Description Responsibilities: Understanding the high-level specification and requirements of functional units of micro-controller and application processor products. Define the Micro-architecture for an unit and developing its RTL, including all design stages. Collaborate with verification team on the TEST plan development for the blocks and verification closure. Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets. Required Skills and Experience: Knowledge with CPU, micro-controllers, memory sub systems and bus architectures is a plus. BS in Electrical and/or Computer Engineering with up to 4 years of experience with RTL design. Experience with Verilog, coupled with design synthesis targeted to achieve specified frequency, power, and area targets. Processor system knowledge including basic understanding of SOC systems as well as operating system software. Great communication & teamwork skills. This position will be 5 days per week office based. cv+6048@hrhome.co.il

Requirements:
Design Verification team lead - Peripheral IP Group (UVM) - (6047) We are looking for a handson Design Verification team lead to drive verification of nextgeneration wired/wireless peripheral subsystems that power Snapdragon platforms.
As a DV team lead in the Peripheral group, you will own verification of complex IPs and subsystems, define and execute a UVMbased verification strategy, and lead a small team of talented engineers to firsttimeright silicon. This role requires proven leadership experience and strong technical expertise.
This is a 5 days onsite position in Haifa.
What youll do: Define verification strategy, TEST plan, and coverage goals for complex peripheral IP and subsystem blocks
Architect, develop, and maintain UVMbased constrainedrandom verification environments
Lead daytoday activities of a small DV team: task planning, code and testplan reviews, mentoring, and technical guidance
Drive debug of complex issues across RTL, testbench, and system level, working closely with design, emulation and validation teams
Analyze and close functional and code coverage, drive quality metrics to tapeout criteria
Contribute to methodology and flow improvements across the Peripheral DV team Minimum qualifications: BSc/MSc in Electrical/Computer Engineering or related field
At least 7 years of handson verification experience using UVM and SystemVerilog
Proven experience in leading and managing a team
Strong background in digital design and SOC /IP architecture High technical proficiency in: UVM testbench architecture (agents, sequences, scoreboards, coverage)
Constrainedrandom, coveragedriven verification
Debugging complex failures in largescale regressions
Scripting ( Python / PERL /Tcl/shell) in a Unix / Linux environment Preferred qualifications: Experience with highspeed peripherals (e.g., USB, PCIe, Display, SerDes, or similar I/O IP)
Knowledge of lowpower, reset, and clockdomain interactions at IP/ SOC level
Familiarity with regression management, metrics, and signoff criteria
Experience working with global, crosssite teams

Requirements:
B.Sc. in Mechanical engineering
Minimum of 4 years of experience in medical device design and development.
Strong understanding of mechanical engineering principles, including materials science, stress analysis, and manufacturing processes.
Analytical, problem-solving, and critical thinking skills.
High verbal communication skills.
Ability to make decisions under pressure.
Great attention to detail and organizational skills.
Proficiency in English and Hebrew
Proficiency in CAD software (SolidWorks, Creo, or similar).
Experience with regulatory requirements (e.g., ISO 13485, FDA QSR).
Ability to work independently and as part of a cross-functional team.

Requirements:
B.Sc. in biomedical/electrical engineering.
At least 5 years of experience in R&D.
Analytical thinking and good planning abilities.
Project management or system level engineering experience.
Good understanding of SW/HW.
Proficiency in Python and MATLAB, and familiarity with Agile project management tools such as Jira.

Requirements:
Degree in Mechanical engineering.
Experience with CAD software.
Proficiency in MS Office.
Proven experience in the engineering field of medical devices - at least 3 years.
Analytical, problem-solving, and critical thinking skills.
High verbal communication skills.
Ability to make decisions under pressure.
Great attention to detail and organizational skills.
Proficiency in English and Hebrew.

Requirements:
5+ years of hands-on experience as a software engineer in high-level programming languages.
Proven track record as a top-tier software engineer, delivering complex technical projects from research to production.
Exceptional problem-solving, critical thinking, and system design skills.
Excellent communication skills and ability to collaborate effectively in a team environment.
Deep experience with software research and practical application in areas such as: reverse engineering, malware analysis, algorithm development, and performance optimizations.
Strong Advantage: Experience with code analysis tools such as static code analysis, dynamic analysis, and data flow analysis.
Bonus Points:
Experience in working with modern backend software architecture.