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which department will you join?
epg is a fast-paced, dynamic, and startup-like group responsible for researching, incubating and developing next-generation technologies and ideas, with a strong orientation towards computer vision, Machine Learning, data, and ai.
the group hosts a diverse team of scientists, engineers and developers to research, realize, and bring to market innovative new products, leveraging cutting-edge technologies, skills and capabilities.
were looking for a backend expert to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out. what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

our platform sw department is looking for a highly driven and dynamic sw customer engineer to join our team and help shape the future of autonomous driving systems.
our team ensures fast and successful integration of mobileye's technologies in customers solutions (car manufacturers / tier1), from the design phase to a car launch, while working closely with internal r&d teams. we're looking for a strong, hands-on, software engineer who is passionately motivated by challenges and excels in troubleshooting hard, complex problems. what will your job look like?
you will work directly with mobileye's development teams on integration into the car manufacturer's system from a Real-Time, safety-critical system aspects.
you will be responsible to provide quick and professional analysis and troubleshooting of advanced customer issues.
support new boards bring up: coding, integration, unit TEST and customer support..
integration with various Embedded systems
 if you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

we are looking for an experienced Hardware Design Engineer with a strong background in high-speed board design to join our radar hw group.
our imaging radar organization develops automotive radar systems that enable advanced driver assistance and fully autonomous driving. the radar hw group has multidisciplinary responsibilities and owns the end-to-end development of all radar hardware which includes: RF and high-speed digital boards, ic packages, mechanical solutions & antenna design
what will your job look like?
design high-speed boards from concept to production
own all design stages: architecture, schematics, layout, modeling, and design reviews
work on boards that include high-speed serdes, lpddr5/4, power circuits, and additional digital interfaces
collaborate closely with RF, mechanical and system teams.

our SOC verification group owns the important and challenging job of verifying mobileye's chip. it is involved from product specification to final SOC delivery, and involves all the system components. the group is made up of few of the best Verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams. what will your job look like:
you'll be responsible for pre-silicon system -level verification of the most cutting-edge ai accelerators and technologies in the automotive field.
define the testplan, develop and run tests on simulation/emulation environments, develop TEST environment and verification collaterals.
you'll have a broad effect on our unique product from the very beginning of the process.

we are seeking a highly motivated system Software manager to lead a team driving the development of next-generation communication software and products, building on our industry-leading nvlink and nvswitch technologies. this role combines technical leadership with hands-on development activities, driving innovation at the core ofdata center ecosystem.
what you will be doing:
lead, mentor, and grow your engineering team while overseeing project planning, execution, and ensuring the quality and performance of all deliverables.
own major features and drive the teams roadmap that aligns with ambitious goals and dynamic customer requirements.
grow the local team while collaborating with a wide range of cross-business unit teams both on-site and locally.
continuously evaluate and identify opportunities to improve processes, infrastructure, and practices to ensure efficient, transparent, and high-quality team execution.
this is a technical leadership role, with active involvement in feature design and implementation.

as a senior software engineer in the gpu networking architecture team, youll lead advanced development and poc efforts for ai infrastructure solutions. you'll be collaborating with experts across distributed ai, deep learning, networking os, virtualization, Storage, and more. come and join us for the cutting edge in gpu networking!
what youll be doing:
drive advanced development and pocs for ai infrastructure solutions in cutting-edge ai networks, integrating innovative software and hardware.
demonstrate team architectural concepts with larger nvidia ai software stacks.
work closely with various groups within nvidia to bring ai network technologies to reality, including gpu and switch hw and sw teams, product as well as fellow architects.

our company is looking for an excellent senior sdk engineer to join the infiniband switch and nvlink fw/sdk group in tel-aviv / raanana. as a senior engineer you will be taking part in designing, implementing and leading major development sdk features, delivering the next-generation networking products. the sdk team develops cutting-edge networking features for cloud, hpc and Storage. we drive the data growth of the worlds biggest companies. with talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced. are you ready for the challenge?
what you will be doing:
collaborate with architecture and different software/fw design teams as part of the software development lifecycle.
design and implement new features in the core of our switch sdk.
work in pre and post-silicon development environments of next-generation our networking products.
gain a deep understanding of system debugging, networking technology, and stacks, as well as the fw/sw relationship.
innovate! bring our sdk switching products to shine in customers view.

we are seeking a highly motivated high-performance system architect to join our team of experts and help shape the future of high-performance and ml / ai computing. our next-generation nvl systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in ai research to high-performance clusters used at almost every industry today, such as car and pharmaceutical. as a high-performance system architect at nvidia, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.
what youll be doing:
define the nvl system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
research of various solutions to enable the next large-scale-high-performance computing clusters. the position spans over various layers from algorithms, software, firmware, and hw.
developing models for simulations and performance testing, analysing the results and development of future hw and sw.
collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

we are now looking for a chip design Verification engineer to join the chip design methodologies team. the team is in charge of the verification methodologies, shared code, training, and embracing new technologies. one of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. this position offers the opportunity to have real impact in a dynamic, technology-focused company.
what you'll be doing:
develop shared verification code and solutions to be widely used by the chip design team.
develop groundbreaking methodologies to create a flawless experience for Verification engineers to keep the focus on new problems.
collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
get in touch with eda vendors to learn about cutting-edge tools/technology and apply them into our verification process.
understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
collaborate with designers, verification specialists to accomplish your tasks.
develop training sessions.

you will be part of our rem (road experience management) department, which is responsible for the automatic high-definition map-making process, which is a key technology in autonomous driving and high-end driving assistance systems. vision-based localization is a key enabler for utilizing and creating the maps. our group is responsible for aligning the map with the world, and reporting detected changes during the drive. our technology is safety-critical, and the code has strict time and memory constraints as it operates in real time. what will your job look like:
develop and optimize computer vision and deep learning algorithms to accelerate data generation and labeling workflows for autonomous driving
apply both classical computer vision techniques and modern deep learning methods to solve large-scale data challenges
collaborate closely with development and annotation teams to enhance automation and ensure high-quality data
own the entire lifecycle from prototyping to scalable deployment within internal pipelines and tools
develop tools to evaluate and analyze algorithm performance, robustness, and operational efficiency

we are now looking for a chip design engineer to join our switch silicon team for verification / design roles. as a chip design engineer at our networking business unit, you'll join a group of passionate engineers to design, implement and verify the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a combined design and verification team which develops some of the switch silicon core units.
micro-architecture for rtl and simulation environment planning for units and modules.
design/verify rtl units/blocks according to arch. specifications under challenging constraints with high orientation to power, area, and performance.
build reference models, verify, and simulate chip blocks/entities according to specifications.
rtl synthesis, timing, supporting verification, and silicon post to activities.
work closely with multiple teams within organizations such as architecture, full chip micro-architecture, be, and fw.

were currently seeking a senior Developer technology engineer, artificial intelligence. would you enjoy researching parallel algorithms to accelerate ai workloads on advanced computer architectures? do you find it rewarding to identify and eliminate system bottlenecks to achieve the best possible performance on pioneering computer hardware? could you be thrilled about an opportunity to partner with the Developer community, working at the forefront of technology breakthroughs that contribute to the success of an industry leader like nvidia? if so, the Developer technology team invites you to consider this role. 
what you will be doing:
in this position, you will research and develop techniques to gpu accelerate workloads in deep learning, Machine Learning or other ai domains.
work directly with other technical experts in their fields (industry and academia) to perform in-depth analysis and optimization of complex ai and hpc algorithms to ensure optimal ai solutions on modern cpu and gpu architectures.
publish and/or present discovered optimization techniques in Developer blogs or relevant conferences to engage and educate the Developer community.
influence the design of next-generation hardware architectures, software, and programming models in collaboration with research, hardware, system software, libraries, and tools teams at nvidia.

looking for firmware engineer to join a team that works on nvidia ethernet switch. you will take part as a fw micro architect in full-cycle firmware development for new and existing products using modern software development tools and approaches.
if you're creative, responsible, hardworking, and autonomous, we want to hear from you!
what you'll be doing:
closely work with sw & hw architecture and different software develop teams to define the fw architecture for new features/improvements.
identify & diagnose high-value data path performance issues.
aim for high quality thinking and creative ways to improve fw performance, scalability and working methodologies.
you will learn how a big software project is operated, maintained, qualified and released, and how hardware and firmware are developed.
collaborate with other nvidia r&d teams around the globe.

seeking a visionary ai Verification engineer to join our chip design methodologies team. were expanding how we use ai across all our verification methods. in this role, youll help us figure out where ai fits best and build the 'brains' behind our tools. youll help us leverage ai, utilizing llms and Machine Learning -to help us debug complex chips faster and more efficiently
what youll be doing
ai ecosystem development: build and deploy an ai verification environment, moving from manual testbenches to automated stimulus generation and coverage closure.
next-gen tooling: develop and integrate ai agents and ml models directly within the verification toolchain to automate intent-to-testbench workflows.
intelligent debugging: create and refine ai-based debug assistants that can analyze simulation failures, categorize bugs, and suggest fixes autonomously.
methodology innovation: research and apply groundbreaking ai approaches (such as reinforcement learning or llms) to address the "state-space explosion" in chip verification.
collaborative intelligence: work with design automation teams and eda vendors to ensure our ai solutions provide end-to-end efficiency from rtl to gds.
leadership & training: act as the authority, training the broader team on how to bring to bear ai tools and "human-in-the-loop" methodologies.
nvidia houses the most forward-thinking minds in the world. are you a creative engineer ready to build the first truly self-verifying chip environment? come join our team and help us define the future of hardware powered by artificial intelligence.

we are now looking for a versatile, fast learner, and highly motivated fe integration and eda tools engineer! as a member of our switch organization, you will be part of frontend integration and eda flows for a highperformance, lowpower switch chip. our fei team drives methodologies, automation, and quality for our frontend implementation and cd/ci, working closely with architecture, design, verification, and backend teams. this position offers you the opportunity to have real impact in a dynamic, technologyfocused company influencing future switch product lines. 
what you'll be doing:
driving frontend integration of major blocks in a pioneering ethernet switch asic, from rtl handoff through synthesis and signoff checks.
building, maintaining, and improving eda flows and methodologies for the switch org (lint, cdc/rdc, formal, synthesis/uls, fedct/fefc and related frontend signoff flows).
working closely with logic design and microarchitecture teams to define integration constraints, clocks/resets, interfaces, and quality targets.
partnering with dv, be, and cad/flow teams to ensure robust, scalable, and efficient frontend implementation across the project.
developing automation and infrastructure (scripts, regression flows, dashboards) to improve productivity, and debuggability.
debugging complex tool, flow, and design issues; driving rootcause analysis and longterm methodology improvements.