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Power the Future with us! We are a global leader in high-performance smart energy technology, with over 3000 employees, offices in 33 countries, and millions of products installed in over 133 countries. Our diverse product offering comprises intelligent solar inverters, battery Storage, backup systems, EV charging, and complete home energy management ecosystems. By leveraging world-class engineering capabilities and with a relentless focus on innovation, we strive to create a world where clean, green energy from the sun is the primary source of power for our homes, businesses, and just about everywhere we thrive. We are a top global leader in smart energy technology. The company's broad range of products encompasses intelligent inverter and Storage systems, revolutionary EV charger, smart energy management solutions and more. Our ASIC controllers stand at the heart of the companys innovation, being both highly flexible and low power, combining digital logic with analog circuits design. At SolarEdge, HW engineers, SW developers and ASIC engineers work together in close collaboration to bring to life a complete solution for the solar energy market. We are looking for an ASIC Digital Design Engineer that is eager to learn and be part of a succeeding team.
What you will be doing:
* Take part in the design of complex mixed-signal devices.
* Collaborate with digital design and Verification engineers in developing digital IPs.
* Work closely with power engineers and SW developers to achieve a deep system understanding.
* Learn how to integrate analog IPs into a digital device.
* Work in a diverse and enriching environment.
Country:
Israel
City:
Herzliya

Power the Future with us! SolarEdge (NASDAQ: SEDG), is a global leader in high-performance smart energy technology, with over 3000 employees, offices in 33 countries, and millions of products installed in over 133 countries. We are seeking a passionate and detail-oriented Student to join our team and contribute to post-silicon validation activities for ASIC devices. This role offers a unique opportunity to deepen your expertise in analog and mixed-signal circuit characterization and contribute to cutting-edge semiconductor development. Responsibilities
* Perform lab characterization of mixed-signal and analog IPs including ADCs, DACs, voltage references (Bandgap), sensing amplifiers, and analog channels
* Analyze measurement data using tools such as Excel and MATLAB, and compare results against specifications
* Develop and document technical reports and measurement procedures
* Implement test automation through coding
* Troubleshoot lab issues and resolve bugs by applying deep analog circuit knowledge
* Collaborate closely with the design team to support validation efforts

Country:
Israel

City:
Herzliya

DustPhotonics is developing a cutting-edge technology in Silicon Photonics which is revolutionizing connectivity and communication in data centers. Silicon photonics is becoming a standard technology used for high performance systems, solving challenges of performance, integration, power and cost. This technology is growing rapidly also in other markets such as Healthcare, LIDARs and other sensors. At DustPhotonics, we are looking to solve the difficult problems, in a smart and simple way, by thinking out of the box, leveraging the knowledge and know-how of the team members, and work as team to create Magic. Our Company culture is characterized by accountability for our ethics, for being fair to every employee, customer, supplier and partner. We believe we must work hard and have fun on the way to success. We welcome you to join our team - Apply for your next career opportunity with us! We are looking for a Silicon Engineering Manager Job description As the Silicon Engineering Manager you will be responsible for improving silicon-photonics yield and performance through data-driven analysis, cross-functional collaboration and proactive issue resolution. You will serve as the key interface between R&D, Process and Production teams, ensuring efficient data flow, rapid issue identification and continuous process improvement across wafer fabrication, device testing, and packaging stages.

Responsibilities:

* Perform silicon process and chip-level data analysis, establishing correlation between chip and wafer performance.
* Lead process debug and yield loss analysis at chip/wafer level, driving root cause investigations and corrective actions.
* Manage engineering approval forum to release production material.
* Collaborate closely with vendors to implement new product tests and resolve technical/process issues.
* Act as a key interface between design, testing, and production teams, ensuring alignment across the product lifecycle
* Oversee and coordinate the transfer of data related to silicon design, testing, fabrication, and characterization between Production and R&D departments.
* Develop and implement data management strategies to ensure data accuracy, security, and accessibility.
* Maintain proper documentation of data transfer protocols, version control, and data integrity checks.
* Support data analysis efforts to improve silicon performance, yield, and quality.
* Ensure compliance with company policies and industry standards related to data security and confidentiality.

Hiring Manager:
Arie Faitelson

What We Are Looking For As a GenAI Security Team Lead, you will lead a team of GenAI researchers, combining both strategic and hands-on, big-picture planning with direct technical contributions. Your primary responsibility will be managing a GenAI-focused team, while fostering a culture of innovation and excellence, providing comprehensive training, guidance, and leadership while ensuring high-quality deliverables. The position balances managerial responsibilities with hands-on technical work (approximately 25%) Key Responsibilities
* Recruit, mentor, and manage a team of GenAI researchers
* Regularly share knowledge with team members and collaborate across departments
* Evaluate and enhance team performance and deliverables quality
* Lead development of automated test harness, continuously evaluating prompts across multiple GenAI models to expose vulnerabilities and measure guardrail effectiveness.



About Alice:
Alice is a trust, safety, and security company built for the AI era. We safeguard the communicative technologies people use to create, collaborate, and interact—whether with each other or with machines. In a world where AI has fundamentally changed the nature of risk, Alice provides end-to-end coverage across the entire AI lifecycle. We support frontier model labs, enterprises, and UGC platforms with a comprehensive suite of solutions: from model hardening evaluations and pre-deployment red-teaming to runtime guardrails and ongoing drift detection.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Developing models for simulations and performance testing, analysing the results and development of future HW and SW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for an experienced DFT Engineer to join an exceptional team of DFT experts to develop the next generation DFT technologies.

As a DFT engineer at the networking group, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

We are looking for best-in-class STA (Static Timing analysis) Physical Design Engineers to join our outstanding Networking DFT team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:
DFT STA execution, from rtl driven constraints and definitions through DFT constraints quality assurance to STA sign-off.
Be part of a unique team of experts who have deep understanding in all aspects of pre and post silicon.
Be exposed and work on a variety of challenging designs, unique DFT solutions that require deep silicon implementation understanding.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part in flows development.

We are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What youll be doing:
Work in a combined design and verification team that develops front-end design for the Switch silicon, GPU and HCA.
Plan and Design Verification units/blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.
Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, and FW-interaction with organization-wide groups.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

Our team propels generative AI forward by building and deploying agentic systems that integrate innovative LLMs with domain tools to expedite HW and SW engineering workflows at scale. We are in search of a top-tier AI Agents Solution Architect to work closely with hardware architects, verification engineers, GPU performance experts, and software developers to develop end-to-end agent flows that drive significant enhancements in simulation analysis, kernel optimization, and developer efficiency.

What you'll be doing:

Develop innovative AI flows to improve hardware and software through collaboration with various engineering roles.

Facilitate co-creation workshops to transform SME rules of thumb into specific assignments, resources, cues, and guidelines. Define success measures, evaluation data, and feedback loops for agents to make a measurable difference in our HW simulation analysis and GPU-kernel optimization workflows.

Rapidly prototype and thoughtfully productize; integrate with internal services, utilize GPU capabilities, remove bottlenecks, and deliver fitting solutions.

Set up evaluation backbone using offline golden sets and online telemetry for confident iterations, cost control, and safe improvements.

Mentor and improve teams through insights in agent orchestration, prompting, RAG, observability, crafting documentation and playbooks for our teams.

Our DOCA team is seeking a highly motivated and hardworking experienced Engineer with hands-on capability technical experience, to design and implementation the SDK of the next generation Data Processing Unit Software, with a wide range of features related to cybersecurity and embedded systems.

This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting data centers across the world. At NVIDIA, We're united in our quest to transform the way Smart Adapters are used.

What you'll be doing:
Work with some of the best engineers to design and implement DOCA SDK and infrastructure.
Responsibility for the E2E development of DOCA SDK features.
Design and develop SDK libraries for networking, storage, cyber security, and high-performance computing.
Work with big companies to solve real issues that require innovation and customer orientation.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

be part of a unique FC team of experts who have deep understanding in all FC aspects, especially integration and STA.

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.