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At Infinidat, a Lenovo company, we empower enterprises and service providers with cutting-edge storage platforms that redefine performance, reliability, and cyber resilience at scale. If you have a strong background in NPI processes, experience in PLM, strong self-learning capabilities, and leading tasks E2E, we’d like to meet you! The NPI engineer will be responsible for the configuration control of INFINIDAT products, and all aspects of NPI processes.

Responsibilities:

* Building and managing Production files: BOMs, Product documentation, working instructions, and drawings.
* Transfer to Production of new products - Full NPI processes.
* Conducting and implementing product changes (ECOs, deviations) and configuration control, managing product lifecycle E2E.
* Ongoing technical support at FTK sub-contractor's production line sites (IL and US) with existing and new products, an initiative for production line continuous improvement.
* Lead the company certifications and compliance maintenance -International and sustainability.
* Work closely with various departments in the company to define manufacturing procedures.

HW Application Engineer - Job description: we are a leading supplier of microcontrollers and security hardware solutions for tier-1 customers in the computing and servers business. It is a self-contained design center, spanning from product management, system and chip architecture, through design, software development, system engineering and production. The group works closely with major customers, primarily key OEMs in the computing space, to develop semi-custom, innovative solutions for a wide range of application platforms. We are looking for a Hardware Application Engineer, to maintain and support our strong collaboration with our customers.
What You Will Be Doing
* Lead customers through all stages of designing their systems based on Nuvoton manageability and security microcontrollers (i.e., BMC, EC, SIO and TPM) from planning till production.
* Respond and resolve customer hardware related issues and requests, reported by the regional support team (FAEs) or directly by customers.
* Work closely with R&D, architects and PMs to provide issue resolutions, workarounds, and implement product features or support tools.
* Key contributor in complex debug tasks for issues found by customers; build debug strategies and hands-on work with the design team through the debug.
* Develop deep knowledge of customer applications and systems, recommend application solutions, design ideas and products to customer design teams.
* Develop and maintain technical documentation (e.g., reference schematics, application notes, design guidelines).
* Provide inputs and participate in next generation ICs definition based on customer inputs.
* Contribute to the definition of innovative and differentiated products.

DRS RADA Technologies , a leading defense company developing and manufacturing life-saving radar systems, is seeking a Complaints & RMA Engineer for its Beit She’an manufacturing facility. The Customer Complaints & RMA Engineer is responsible for the engineering aspects of customer complaints and Returned Material Authorization (RMA) processes. The role involves conducting failure Analysis, performing root cause analysis, leading corrective and preventive actions, and driving continuous improvement of product quality and reliability. The position requires close collaboration with cross-functional teams and customers worldwide to ensure professional, rapid, and effective resolution of quality issues. Responsibilities
* Conduct failure investigations for products returned through RMA processes and customer complaints.
* Analyze product failures using engineering tools and methodologies to identify root causes (Root Cause Analysis).
* Define and lead Corrective and Preventive Actions (CAPA) in collaboration with Engineering, Manufacturing, Quality, and Purchasing teams.
* Prepare detailed failure analysis reports, document findings, and present conclusions to relevant stakeholders.
* Provide engineering ownership of customer complaint investigations through to technical closure.
* Communicate with customers in Israel and internationally, presenting investigation results and providing technical recommendations.
* Support NCR, MRB, and quality investigation processes as required.
* Analyze recurring failure trends and lead initiatives to improve product quality and reliability.
* Coordinate with testing laboratories, suppliers, and subcontractors to perform testing and validate findings.
* Participate in internal and external quality audits as required.
* Ensure compliance with company procedures, quality standards, and applicable regulatory requirements.

We are global, with HQ in NYC and R&D centers in Tel Aviv, New York, Finland, Berlin, Belgium and San Diego. We work in a fast-paced environment and have a lot of challenges to solve. If you like to work in a huge scale environment and want to help us build products that have a huge impact on the industry, and the web - then your place is with us.
What you will do:
Develop and improve models that analyze millions of videos and images every day across the web, Smart TVs, YouTube, Facebook, Twitter, Instagram, TikTok and more to detect the content categories they are about.
Work alongside experienced data scientists and engineers in a cutting-edge environment, contributing to advanced ensembles of models at huge scale.
Participate in the full development cycle - from research and experimentation through to deployment - gaining hands-on experience with production ML systems.
Leverage AI-powered tools and assistants as part of your daily workflow to accelerate research, coding, and analysis.
Help advertisers avoid negative or irrelevant content and target what's most relevant to their brand, keeping the web free for everyone.

We are seeking a Package Layout Design Engineer to join our hardware team and contribute to the physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will execute package layout tasks from floor planning through tape out and manufacturing release, working closely with senior engineers, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet performance, density, and reliability targets.

Key job responsibilities
- Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
- Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
- Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
- Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
- Support die-level RDL routing and bump planning in coordination with ASIC physical design teams to help co-optimize the die-package interface.
- Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels under guidance from senior engineers.
- Assist in maintaining package stack-up definitions in collaboration with SI/PI and materials engineering teams.
- Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
- Follow and help refine package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance.
- Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout - impedance-controlled routing, power plane optimization, and critical net shielding.

Were searching for sharp engineers to lead cutting edge products, re:inventing super computers and deploy our new EFA (Elastic Fabric Adapter) network protocol into the largest public cloud on the planet! starting from the identification and definition of project requirement, defining SW and HW interfaces, feature development and deployment, to operation support on a very large scale.

We're looking for a Design Verification Team Lead - a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Nitro system SoC, the foundation of AWS's virtualization, networking, and storage offload infrastructure.

It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.

It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA.

It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.

It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development.

Key job responsibilities

- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA).

- Verify IO sub-system features, including interconnect protocols and various accelerator engines.

- Develop and debug C embedded SW as part of hardware-software integration verification.

- Build and maintain UVM-based verification environments for various clusters and sub-systems.

- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.

- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).

- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.

- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.

- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.

We are looking for a Nitro System Manufacturing Integration Lead Engineer to be part of defining, shaping, and implementing manufacturing flows, test definitions, and card-to-server integration processes for Nitro-based platforms. This includes to be part of the manufacturing flow architecture, production test strategy, process stabilization, and yield optimization bridging system design intent with high-volume manufacturing execution.

Key job responsibilities
As a System Manufacturing Integration Lead Engineer, in the Nitro team, you will own the end-to-end manufacturing flows for accelerator card-to-server integration across manufacturing partner facilities driving the process from initial definition through stabilization into a scalable, high-yield mass production operation.

Key responsibilities include:
- Architect manufacturing flows - be part of the complete card-to-server integration sequence, including every process step, quality gate, and decision point from sub-assembly through system integration and tests.
- Define test strategy - be part of determining what to test, when, and at which station, covering card-level functional tests, post-integration validation, firmware provisioning, and first power-up diagnostics.
- Establish classification criteria - be part of determining pass/fail thresholds and test exit gates to maximize yield and minimize material waste.
- Drive process stabilization - work directly and on-site with manufacturing partners to implement, debug, and iterate on manufacturing flows from early builds through a locked, repeatable production process.
- Design alternative flows - develop parallel manufacturing paths to address real-world constraints such as component availability gaps, deferred card integration, and hub-based assembly models.
- Own process documentation & KPIs - maintain manufacturing flow baselines, drive process change control, and track yield, first-pass rate, cycle time, and defect Pareto.
- Lead cross-functional coordination - serve as the single point of ownership across hardware engineering, firmware, test/vetting, thermal, mechanical, and operations teams for Nitro-based accelerator servers built at scale.

Were searching for a Lab Technion Student who will be responsible for the installation, configuration, maintenance, and troubleshooting of our Linux-based server infrastructure, as well as managing various network services and components.

Student will have at least 4 semesters remaining in their degree. The ideal candidate will posses a strong passion for learning new things and the ability to quickly put that new knowledge and skills into practice. You will have the ability to perform basic troubleshooting for hardware, software, and networking issues without guidance.

We're looking for Electrical Engineering graduates to join the Pre-Silicon Verification Team based in Haifa.

As a Junior Pre-Silicon Verification Engineer, you'll work at the heart of chip development, collaborating across teams to ensure our semiconductor platforms meet the highest standards before they reach production.
IO verification team will expose you to the most advanced technologies , as we lead the market with our leaving devices - youll soon have to expertise most advance protocols

A day in the life
In this role, you'll engage in pre-silicon verification work that connects every phase of our product development journey- from initial product definition through firmware and software development.
You'll collaborate with hardware designers, software engineers, and cross-functional teams to validate complex semiconductor architectures and protocols.
Your days might include developing and executing verification test plans, analyzing simulation results, troubleshooting design issues, and participating in design reviews.
You'll work with advanced verification methodologies and tools, gaining exposure to cutting-edge technologies that define the next generation of cloud infrastructure.

We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
Holistic view of the entire interconnect, from the DIEs metals, through the Package, to the PCB traces, and all the way to the peer device.
In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Labs Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The teams work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGAs substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.
We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years' experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain.

Key job responsibilities
Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.